DAC5652A: When in Power-down mode (not ZERO)

Hey Naoki,

I see in your scope shot that your DAC clock is running right when the DAC outputs a signal. From what i understand, the DAC will still output data if the input clock is running. Therefore, while the clock is running, the dac will output garbage if there is noise on the input data line. Try turning off the input clock and verifying that there is no data on the output before asserting SLEEP mode. Let me know your results.

Thanks

Yusuf

Hello Yusuf,

Thank you for your reply.
I will ask the customer to check the output with SLEEP is Low and no CLK.
If I got a result I will let you know.
But when after turning on the power with SLEEP is Low and no CLK, the DAC output is indefinite data, right?

Best Regards,
Naoki Aoyama

Hello Yusuf,

I got a verification results. I attach the file.

DAC5652A_verification.pptx

The customer want to output zero during from power on until outputting an arbitrary value.

Do you have any good ides that satisfy the request?

Best Regards,

Naoki Aoyama

Hello Yusuf,

Is there any update?

Regards,
Naoki Aoyama

Hey Naoki,

I am looking into this currently. I will respond before the end of the day.

Thanks

yusuf

Can you send me the customer schematic and PCB layout files?

Yusuf

Hello Yusuf,

I will ask the customer to give us the schematic and layout.
Perhaps, the customer do not open that information.
Could you tell me your e-mail address?

Regards,
Naoki Aoyama

Hi Naoki,

Can you ask the customer to power the DVDD to 3.3V and Gnd(0V) the AVDD at the very beginning. Apply the clock signal and send mid code to the DAC wait for 5 clock cycles and apply 3.3V to AVDD and DAC should output 0V.

Regards,
Neeraj

Hi Neeraj,

Thank you for your reply.
Yes, I can.
I will ask the customer to try your idea.

Regards,
Naoki Aoyama

Hi Neeraj,

The customer need modify their prototype board for applying the new power up sequence.
So, they can not try your idea immediately.
Could you give them the waveform that result of applying your idea?
They want to see the output become 0.

Regards,
Naoki Aoyama

Hello Neeraj,

Because the customer can not try your idea immediately.
Could you give them the waveform that result of applying your idea?

They have one more question. Is there any limitation of the DVDD and AVDD
power up sequence?

If we answer the above question, they will apply your idea and close this matter.

Best Regards,
Naoki Aoyama

Hi Naoki,

The Absolute max spec for voltage difference between AVDD and DVDD is -4V to 4V. The Device will still be within the Absolute max spec when 3.3V is applied to DVDD while AVDD was still at 0V.

Regards,
Neeraj

Hello Neeraj,

Thank you for your reply.
I understood there is no power up sequence.

Could you check your idea as below by the EVM of yours?
------------------------------------------------------------------------------------------------------
>Can you ask the customer to power the DVDD to 3.3V and Gnd(0V) the AVDD at the very beginning. Apply the clock signal and send mid >code to the DAC wait for 5 clock cycles and apply 3.3V to AVDD and DAC should output 0V.
-----------------------------------------------------------------------------------------------------
It may take your time, but check it please.

Best Regards,
Naoki Aoyama

Hello Neeraj,

Could you check your idea by EVM?

Please tell me why you can not.
I will persuade the customer to check it by himself.

Regards,
Naoki Aoyama

Hi Neeraj,

Is there any update?

Regards,
Naoki Aoyama