Hello TI,
I studied ADS7057 and question about SPI communiation.
I saw the separate sheet show SPI clock need read 18 CLK, usually SPI is 8 clock in cycle. So we need to use 24 CLK format to read it, right?
There is effect SPI communiate efficiency? If yes, could you advise me better solution or other user how to solve this question, thanks!
Hello,
If your host controller cannot support 18 read cycles, then there are other options
Using 24 clock cycles is an option, but this will add time to your throuput rate, decreasing how fast you receive conversion results.
This device sends out a leading zero, then 14 bits of data, followed by zeros. If you read out only the first 16 cycles and ignore the rest of the data, you may maintain the origianl throughout. Note that if you do this, you will still need to send out 18 clock cycles, just ignore, or note read the last bits. If you can support this, this would probably be the best option.
If doing this, keep in mind that a leading 0 is output on the SDO pin on the CS falling edge. The most significant bit (MSB) of the output data is launched on the SDO pin on the rising edge after the first SCLK falling edge. In other words, after CS low, the device needs to see a falling edge on SCLK, not until after this do the rising edges of SCLK output the data bits.
Regards
Cynthia
