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ADS1202: ADS1202 and implementing the SINC3 filter (as per SBAA094)

Part Number: ADS1202
Other Parts Discussed in Thread: AMC1210,

I am using the VHDL code provided in the SBAA094 note.  The output of the VHDL module is 25 bits (0-24).

If I intend on using a clock frequency of 10MHz, and a decimation factor of 128, which of the 25 output bits do I want?  That is, which bits are most significant, and what do I do with the rest?

  • Hi Richard,

    In that application note, if I remember correctly, we just kept everything in 32-bit register. There is a description in the AMC1210 datasheet regarding looking at data from modulators like the ADS1202 in '16-bit' mode (see 16-bit data shifting on page 22)., by just keeping the most significant bits and discarding the 'noise'. In your case, assuming you wanted to keep the 16 most significant bits, you would take b24 through b9.