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DAC082S085: DAC082S085 SCLK ratings & lower-limit parameters

Leo Chow
Expert 3120 points
Part Number: DAC082S085

Hi,

with reference to datasheet section 7.6(Timing Requirements) of DAC082S085, seems that SCLK cycle time Tmin is rated at 33ns hence carrying Fsclk of 30Mhz, May i know what is the possible lowest SCLk we could implement in our design system? Assuming we were to work at << 4MHz, what are the potential outcome we may foresee & is it okay for us to operate at this frequency range? Thanks.

Regards,
Leo

  • 0
    TI__Mastermind 46290 points
    Leo,

    There isn't really a limitation to how slowly the SCLK can operate. Internally the device interface does not have any significant intelligence like an oscillator or timer to decide that a frame has taken too long. The implementation is just very simple latching mechanisms based on the described threshold voltages for SCLK and SYNC, with limitations for how quickly the signals can slew and still be detected reliably / appropriately.