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ADS7223: interface timing

Lutz Naumann
Expert 6110 points
Part Number: ADS7223

Hello Team,

I do have a question regarding the interface ting of ADS7223. It will be connected to an FPGA. The ADC will operate in pseudo diff configuration and full-clock-mode will be enabled. Attached a simulation of the planned timing. We want to combine the CONVST and RD signals. SDO and SDA are driven with 1 or 0 on purpose in the attached example. On thing to note, which is not yet shown in the timing, are the 12ns of CONVST_RD bevor the first edge of SCLK. This will be implemented.

 

According to the datasheet our understanding is that when combining CONVST_RD the nCS must be set to 0 when switching CONVST_RD to 1. Is this understanding correct? We could not find a timing restriction between nCS->0 to CONVST_RD->1. In our example we have both transition at the same time. Is there a timing restriction?

 

Furthermore is the timing for CONVST_RD->0 for reading the data correct or does it have to happen half or a full SCLK earlier? In the example with bit count 17 we expect the MSB or the ADC channel to be reported already.

 


 

many thanks

Lutz

 

  • 0
    TI__Guru**** 168445 points
    Hi Lutz,

    With the ADS7223 and its counterparts, the rising CONVST opens the S/H switch. This action is asynchronous and is not influenced by either SCLK edge - the actual start of conversion is though, that is the 12nS (t1) in the datasheet. The RD is qualified on the first falling SCLK edge (+/- 5nS tS1 and tH1), so the down side of your intended timing is that you will get the previous conversion results being output while the current conversion is taking place. If you truly want to operate in full clock mode, you would need to separate CONVST and RD as shown in Figure 2.
  • 0 in reply to Tom Hendrick
    TI__Expert 6110 points

    Thanks Tom,

    With CONVST -> 1 at the next riding SCLK edge the conversion will start. We were planning to wait until this is complete before RD->0. We actually wanted to read the signal immediately after the conversion is complete. With the combined CONVST_RD ->1 signal the conversion would start and once complete with the CONVST_RD->0 we want to read the data. According to the picture on page 30 of the datasheet this should be possible. 

    The question would be how many SCLK cycles do we have to wait until before the read register has been updated.

    thanks

    Lutz

  • 0 in reply to Lutz Naumann
    TI__Guru**** 168445 points

    Hi Lutz,

    Sorry for the confusion - if you intend to use the CHID bits, you can send RD+CONVST low with the 23rd rising SCLK.  If you are taking DATA only, it would be the 25th.

  • 0 in reply to Tom Hendrick
    TI__Expert 6110 points

    Thanks Tom,

     

    one question still remains and this is wrt. to nCS signal when combining the CONVST_RD. Is it really necessary to drive nCS->0 bevor the setting combined CONVST_RD -> 1? Or is it sufficient to set the nCS->0 sometime later but ensuring to be set low bevor the 22nd clock?

     

    many thanks

    Lutz

  • 0 in reply to Lutz Naumann
    TI__Guru**** 168445 points
    Hi Lutz,

    The CONVST portion of the cycle does not need to see /CS low, but you would have to set it low before reading the conversion results (i.e. before CLK 22). If you are not sharing the bus with anything else, you can tie /CS low, saving a pin on the FPGA.
  • 0 in reply to Tom Hendrick
    TI__Expert 6110 points

    Tanks Tom,

    this was what we needed.

    Lutz