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TSW54J60EVM: TSW54J60EVM configuration for 1 GSPS

Part Number: TSW54J60EVM
Other Parts Discussed in Thread: TSW14J57EVM, ADS54J60EVM, LMK04828, ADS54J60


I need to configure the TSW54J60EVM board using the ADS54Jxx GUI v1.8 so that the sampling rate would be 1 GSPS.

As far as I understand, I need the ADC working in 4211 mode and the LMK providing the proper clocks.

What frequencies do I need from the LMK?

Could I please be provided with LMK and ADC configuration files for this case?

I found a lot of configuration files in \Texas Instruments\ADS54Jxx EVM GUI\Configuration Files\ folder but can't figure out which one may suit my need, if any.

As far as I guess, the lane rate for 1 GSPS sampling rate is  1 * 16 * 1.25 * 1000 / 4 = 5000 MHz, but according to the datasheet page 41, the lane rate is 10.0gsps. Is that because the ADC is dual channel and the rate in the spec is given for 2 ADCs mode?

Should the FPGA JESD reference clock be 5000/20 = 250 MHz?
Should the FPGA core clock be 5000/40 = 125 MHz?

Thank you in advance,

Kind regards,

  • Hi Ilya

    The TSW54J60EVM can operate using on-board or external clocking. When on-board clocking is used the closest available sample rates to your target of 1 GSPS are 983.04 MSPS and 1024MSPS.
    To configure the board follow the steps in section 2.3.1 of the TSW54J60 Evaluation Module user guide.
    The standard procedure uses the file for 983.04 MSPS. If desired you can substitute the file for 1024 MSPS instead.
    These files will configure the EVM for operation with the TSW14J56EVM or TSW14J57EVM.

    If you need exactly 1 GSPS you will need to use an external 1 GHz clock and configure the board appropriately for that condition. Section 5.1.2 of the user guide describes the configuration steps needed in this case.

    If you are using a different capture platform such as an FPGA development board from Xilinx or Intel you may need to adjust the FPGA clock dividers slightly. Please let us know which capture board you are using.

    Best regards,
    Jim B
  • Hi Jim

    Thank you for your reply.

    983.04 MSPS would be ok, the board is Xilinx VC707.

    What frequencies should the LMK generate? It would be great if the correct LMK settings for the case could be posted here.

    We tried to calculate the lane rate for 4211 mode as follows: 1 x 16 x 1.25 x 983.04 / 4 = 4915.2 MSPS and we are not sure it's correct.
    Could you please show the correct way to calculate the lane rate for this case?

    Does refclk = lanerate/20 and coreclk = lanerate/40 ?

    Thank you in advance,

    Kind regards,

  • Hi Ilya
    If you are using the Xilinx VC707 then the TSW14J10EVM will be of interest to you. It supports operation of the TSW54J60EVM and ADS54J60EVM using 8224 mode and our existing firmware build which will be provided from High Speed Data Converter Pro software.
    In 8224 mode with Fclk = 983.04 MHz the serial data rate is 4915.2 Gbps.
    For that line rate the FPGA clocks need to be as follows (from Section 6, page 15 of the TSW14J10EVM user guide):
    REFCLK = Lane rate / 20 and Core clock = Lane rate / 40 when lane rate is between 3.2G and 10.3125G.
    At that clock frequency the LMK04828 PLL2 VCO is running at 983.04 MHz x 3 = 2949.12 MHz.
    REFCLK = 245.76 MHz (this is PLL2_VCO / 12) is on FMC pins D4 and D5 - this corresponds to DCLKOUT0 on the LMK04828.
    Core clock = 122.88 MHz (this is PLL2_VCO / 24) is on FMC pins G6 and G7 - this corresponds to DCLKOUT12 on the LMK04828.
    DCLKOUT0 divider is already equal to 12 so that stays the same. You will need to modify the LMK04828 configuration file "ADS54J60_LMF_8224.cfg" to enable DCLKOUT12 as LVDS with divide by 24.
    I hope this is helpful.
    Best regards,
    Jim B