DAC3484EVM: used with TSW1400

Hi Ron,

Regarding your questions:

Ron Breding said:

I'm not seeing how to set up the DACCLK based on this data rate. 

The DACCLK depends on the final interpolation setting that you intend to use. If you want to have 2x interpolation, then the DACCLK is 32MSPS per channel of baseband data * 2 = 64MSPS. If 4x, then 128MSPS.

Ron Breding said:

1) How does this setup for the TSW1400 output 4 tones? (i.e.2 DATACLK cycles output 4 channels of data per DDR at 64MHz) 

This is taken care of by the FPGA clock setup from the DAC3484EVM to generate the necessary FPGA reference clock and for the DATACLK from the DAC3484.

Ron Breding said:

2) Does the HSDR Pro software only output 1 channel? All 4 for the same tone setup per channel?

The default, easiest to use mode is to generate I/Q tones for the 2 sets of 2 channels. CH A = I, Ch B = Q, CH C = I and CH D = Q. These channels gets the same tone (or multi-tone) from HSDC PRO. you may customize your own pattern through .csv file loading within HSDC PRO. 

Ron Breding said:

3) Can I use the on-board 19.2MHz oscillator to generate the DACCLK necessary for 1x, 2x, 4x, 8x, and 16x interpolation?

Yes you can. the default DAC3484 GUI directory have examples on generating clocks such as 983.04MHz and 1228.8MHz. You can check with the clocking forum on the setup for the CDCE62005.

Ron Breding said:

4) How do I avoid "beat" frequencies in the output waveform caused by the FIFO input DATACLK vs the FIFO output clock and DACCLK?

I am not sure what you mean. The FIFO should be reset one time by various methods discussed in the datasheet. There should not be any beat frequencies assuming all the logics are running correctly.

here are some information that you may refer to gain more insight.

-Kang

"    Ron Breding

I have a 32MHz input data rate for all 4 channels.  I'm not seeing how to set up the DACCLK based on this data rate."

If the signal sample rate on the input side is 32MHz, the input DATACLK is 64MHz per DDR clocking of all 4 channels.

"  Kang Hsia

The DACCLK depends on the final interpolation setting that you intend to use. If you want to have 2x interpolation, then the DACCLK is 32MSPS per channel of baseband data * 2 = 64MSPS. If 4x, then 128MSPS."

Are you saying to multiply the input sample rate by the interpolation factor in order to achieve the correct DACCLK?

2x = 64MHz, 4x = 128MHz, 8x = 256MHz, 16x = 512MHz

Is that the same as the Fsample?

"  Kang Hsia

This is taken care of by the FPGA clock setup from the DAC3484EVM to generate the necessary FPGA reference clock and for the DATACLK from the DAC3484."

Are you stating that the DATACLK is derived in the FPGA fabric from the FPGA_CLKOUTP/N output from the DAC3484EVM?  That makes the most sense to me.

"    Ron Breding

   3) Can I use the on-board 19.2MHz oscillator to generate the DACCLK necessary for 1x, 2x, 4x, 8x, and 16x interpolation?

"  Kang Hsia

Yes you can. the default DAC3484 GUI directory have examples on generating clocks such as 983.04MHz and 1228.8MHz. You can check with the clocking forum on the setup for the CDCE62005."

If I wanted an Fdac = 524.544MHz (i.e. 32.784MHz * 16), then would I need to generate this frequency from the U2 output from the CDCE62005?  It's unclear to me as to how the synthesizer block sets the frequency.  I see the VCO select operates a VCO range, but I don't completely understand the math to the output for my required result.  

8.2.6 Computing The Output Frequency
Figure 16 shows the block diagram of the CDCE62005 in synthesizer mode highlighting the clock path for a
single output. It also identifies the following regions containing dividers comprising the complete clock path
• R: Includes the cumulative divider values of all dividers included from the Input Ports to the output of the
Smart Multiplexer (see Input Block for more details)
• O: The output divider value (see Figure 18 in Output Block for more details)
• I: The input divider value (see Synthesizer Block for more details)
• P: The prescaler divider value (see Synthesizer Block for more details)
• F: The cumulative divider value of all dividers falling within the feedback divider (see Synthesizer Block for
more details)

With respect to Figure 16, any output frequency generated by the CDCE62005 relates to the input frequency
connected to the Synthesizer Block by Equation 1.
Fout = Fin * F / (R * I * O)                                                                                                                                                              (1)

Equation 1 holds true when subject to the following constraints

1.750 Ghz < O x P x FOUT< 2.356 GHz                                                                                                                                      (2)

The comparison frequency FCOMP is:
40 kHz ≤ FCOMP < 40 MHz (3)
where:
(4)
NOTE
This device cannot output the frequencies between 785 MHz to 875 MHz

(See Figure 15 and 16 in the cdce62005.pdf datasheet)

I see Figure 16 that describes Fout = Fin * F / (R * I * O), where it appears that the VCO output frequency = O * P * Fout

If Fin = 19.2MHz, setting F = 683, R= 1, O=1, I=25 I can acheive 524.544MHz on Fout.  The problem is that 683 is not an option for the F value as this is a drop-down menu only. (i.e. 683 = 3 * 3 * 3 * 5 * 5)

Is there a GUI to set up an output frequency on the CDCE62005?  The CDCE62005 Control tab   I want Fout = Fdac = DACCLK = 524.544MHz, 262.272MHz, 131.136MHz, 65.568MHz, 32.784MHz corresponding to x16, x8, x4, x2, or x1 interpolation.

and...

FPGA_CLKOUT = U3 = 262.272MHz always to be synchronous with U2 output all sourced from the 19.2MHz clock input on the secondary reference.

"  Kang Hsia

I am not sure what you mean. The FIFO should be reset one time by various methods discussed in the datasheet. There should not be any beat frequencies assuming all the logics are running correctly."

If the DATACLK is not synchronous to the DACCLK the FIFO read/write relationship cannot be maintained without a fixed phase relationship.  Your answer to my 1st question seems to imply this relationship.