Other Parts Discussed in Thread: ADC12J4000
Hello,
Our original FPGA(Xilinx KU060) board is combined ADC12J4000EVM via FMC.
I'm checking the received data from ADC12J4000(JESD204B) using ChipScope on FPGA.
It seems the Ramp_Test_Data is incorrect.
I can see the proper K_symbols on ILAS data,
but I cannot confirm the Dx.y_data on ILAS each frame data is correct or not.
Is the Dx.y_data equal to the Ramp_Test_Data?
I attach the Chipscope data of FPGA transceiver's rxdata.
So, Is ILAS data correct?
If not, Please advise, the correct data(bits) on ILAS and the user_(Ramp_)data.
[Our system's configuration] :
ADC12J4000 : LMF=8,8,8(Bypass,No_Decimation,DDR), Fs=3.2GSPS(Line_Rate=6.4Gbps)
JESD204B on FPGA: GTH_transceivers(not using JESD204B_IP) 16bit data bus
Running Ramp_Test_data on ADC12J4000
[ILAS data]
I set "0x55" to the JESD_DID(0x203) register using GUI, but seeing "0xaa" above.
[Ramp_Test_data]
00, 01, 02, 1C?, 04, 1a?, ....