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ADC12J4000EVM: JESD204B output data of ADC12J4000

Part Number: ADC12J4000EVM
Other Parts Discussed in Thread: ADC12J4000, TEST


Our original FPGA(Xilinx KU060) board is combined ADC12J4000EVM via FMC.

I'm checking the received data from ADC12J4000(JESD204B) using ChipScope on FPGA.

It seems the Ramp_Test_Data is incorrect.

I can see the proper K_symbols on ILAS data,

but I cannot confirm the Dx.y_data on ILAS each frame data is correct or not.

Is the Dx.y_data equal to the Ramp_Test_Data?

I attach the Chipscope data of FPGA transceiver's rxdata.

So, Is  ILAS data correct?

If not, Please advise, the correct data(bits) on ILAS and the user_(Ramp_)data. 

 [Our system's configuration] :

ADC12J4000 : LMF=8,8,8(Bypass,No_Decimation,DDR), Fs=3.2GSPS(Line_Rate=6.4Gbps)

JESD204B on FPGA: GTH_transceivers(not using JESD204B_IP) 16bit data bus

Running Ramp_Test_data on ADC12J4000

[ILAS data] 

I set "0x55" to the JESD_DID(0x203) register using GUI, but seeing "0xaa" above.


00, 01, 02, 1C?, 04, 1a?, ....


  • Hi user
    I am reviewing the information you have provided. I will respond in more detail by end of business Monday.
    Best regards,
    Jim B

  • Hello,

    Concerning  our "proper K_symbols on ILAS data",

    I inform more details of captured ILAS pattern.

    I attach the whole ILAS  data below,

    The position of K seems to be correct to JESD204B_5.3.3.5.

    [ ]==Chipscope_scale

    [151]R(K28.0), [166]A(K28.3), [167]R(K28.0) Q(K28.4) 

    [182]A(K28.3), [183]R(K28.0)

    [198]A(K28.3), [199]R(K28.0)

    [214]A(K28.3), [215---]Ramp_Test_Data

  • I think this issue resolved.

    I changed the polarity of rx_lanes on Xilinx's GTH_transceivers

    to match to the ADC12J4000EVM's rx_lane.

    The ADC12J4000EVM-SCH shows below,

    Dx_"N" <--> DPx_M2C_"P".

    Dx_"P" <--> DPx_M2C_"N".

    I attach the ChipScope(End_of ILAS->Ramp) after changing.