Other Parts Discussed in Thread: DAC8560,
Let me just confirm a serial interface specification of DAC8551 and DAC8560.
/SYNC falling edge to SCLK rising edge is defined as 0ns(MIN) in the datasheet.
But the MAX value is not available.
If /SYNC falls at SCLK falling edge like the below figure, which timing is DIN first sampled at, A, B or C?