Other Parts Discussed in Thread: AMC1303M0510
Hi,
I am using the AMC1303M2520 and When I read the datasheet about the description and Diagram.
1. In 8.4.1 Fail-Safe Output, the description shows that "In both cases, the steady-state logic 1 occurs on the DOUT output with a delay of two clock cycles after the event of either exceeded common-mode input voltage or missing AVDD." But at the "Figure 48. Fail-Safe Output of the AMC1303", it shows 4 cycles after Over voltage.
So may I know which one is correct?
2. I would like to confirm with you that, does it mean the 16bit can represent 0x1 to 0xFFFE for normal read back value. If 16-bit all 0x0000 and 0xFFFF represent abnormal or error(1.AVDD abonormal, 2. Overvoltage error).
3. Is the clk and Data will be continues generated? How can the receiver side to determine the start bit or no start bit concept. Only if countering continues 256 cycles?
Thanks.