AMC1303M2520: Datasheet mismatch on digital interface decription and diagram

LI XIANG

Part Number: AMC1303M2520
Other Parts Discussed in Thread: AMC1303M0510

Hi,

I am using the AMC1303M2520 and When I read the datasheet about the description and Diagram.

1. In 8.4.1 Fail-Safe Output, the description shows that "In both cases, the steady-state logic 1 occurs on the DOUT output with a delay of two clock cycles after the event of either exceeded common-mode input voltage or missing AVDD." But at the "Figure 48. Fail-Safe Output of the AMC1303", it shows 4 cycles after Over voltage.

So may I know which one is correct?

2. I would like to confirm with you that, does it mean the 16bit can represent 0x1 to 0xFFFE for normal read back value. If 16-bit all 0x0000 and 0xFFFF represent abnormal or error(1.AVDD abonormal, 2. Overvoltage error).

3. Is the clk and Data will be continues generated? How can the receiver side to determine the start bit or no start bit concept. Only if countering continues 256 cycles?

Thanks.

over 5 years ago

0 Tom Hendrick over 5 years ago

TI__Guru**** 168445 points

Hi Li Xiang,

I'll get a resolution for the apparent mis-match in the text versus the diagram in the AMC1303M2520 datasheet. There is no 'start or stop' bit associated with these devices, it's just a continuous data stream. If the AVDD supply is missing, the output data behavior would be as shown in Figure 2. DOUT will be a constant 1 and after 256 clock cycles, the output clock will also go to a static 1 state. The same behavior applies in the case of exceeding the common mode voltage. In the case of reaching the full scale input, the clock will continue to run, but the output will pulse high (when FS- is reached) or pulse low (when FS+ is reached) once every 127 CLKOUT cycles.

0 LI XIANG over 5 years ago in reply to Tom Hendrick

Intellectual 445 points

Hi Hendrick,

Thanks for your reply. and Wait for your update on the delay cycle 2 or 4.

Besides, The AVDD error and Vin >= Vcmov are all output 0xFFFF. so there is no way to determine which error, right?

If any, please let me know.

Thanks a lot.

0 Tom Hendrick over 5 years ago in reply to LI XIANG

TI__Guru**** 168445 points

Hi Li Xiang,

Yes, that is correct, missing AVDD and exceeding the VCM voltage both produce the same output.

0 LI XIANG over 5 years ago in reply to Tom Hendrick

Intellectual 445 points

Hi Hendrick,

Thanks for your reply and explain.

Please help to followup the cycle problem and thanks a lot.

0 Tom Hendrick over 5 years ago in reply to LI XIANG

TI__Guru**** 168445 points

Hi Li,

As soon as I get confirmation from the digital design team, I will let you know if it's 2 or 4 clock cycles.

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AMC1303M2520: Datasheet mismatch on digital interface decription and diagram