This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS61B29: LVDS clock input specification clarification

Part Number: ADS61B29
Other Parts Discussed in Thread: ADS4129

Both ADS61B29 and ADS4129 datasheets specify a MIN sine wave amplitude for clock input of 0.3v and 0.2v, respectively. However for a LVDS clock input only a TYP amplitude of 0.7v is specified. Given that many LVDS sources have output amplitudes well below 0.7v p-p, we would like to understand what the actual minimum LVDS amplitude requirement is so we know how much margin we will have with various LVDS clock drivers.

Please answer for both ADS61B29 and ADS4129.

  • Hi Sam,

    the minimum is based on the performance of the ADC (SNR and SFDR). If you look at the datasheet performance plot, there are plots regarding the SNR and SFDR performance vs. input clock amplitude

    The minimum was set when the SNR and SFDR was near the dropping point. This is due to the lower swing weakens the sampling point instances and causes jitter in the sampling decision point.

    If the clock driver also suffer of reduction in clock swing across temperature, then the system may have no margin at all. It is best to introduce the optimal level of swing to achieve best SNR/SFDR performance. 

  • Thanks, I really appreciate your fast reply. Perhaps a footnote under the dc specs table or a brief discussion of this issue in the clocking section of the datasheet would be appropriate. I was thinking of this input in terms of it being a threshold issue rather than having quite so much effect on the sampling performance.