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ADS1217: DRDYn signal is always "clocking" (high = 20us, low = 30ms)

Fausto Bartra1
Intellectual 435 points
Part Number: ADS1217

Everything seems to be working ok,

but I dont know why the DRDYn pin is always driving this signal even after power up!!!

Below pin status: (I am not issuing any commands to ADC)

CSn = high

SCLK = low

CLK = 8MHZ

DIN =  low

DSYNC = high

DOUT = low

POL = low

RESETn = High

DRDY = "clocking" (high = 20us, low = 30ms)

Register settings:

REG0 = 0x0C = fosc/128 + Int Vref enable + Int Vref = 2.5V + Buffer disable + MSb transmitted first

REG 9 = 0x47 = Unipolar + Auto setting mode + Decimation default D10 to D8 = 7

Any suggestions?

Thank you

Fausto Bartra

  • 0
    Intellectual 435 points
    also, PDWNn = High
    Thank you
  • 0 in reply to Fausto Bartra1
    TI__Guru** 113765 points
    Hi Fausto,

    The default data rate for the ADS1217 is 10sps for a 2.4576 MHz clock. If you are using an 8 MHz clock you will see an output rate approximately 3.25 times faster (8/2.4576) which would be a period of about 32ms. This means that the conversion result is updated approximately every 32.5ms.

    DRDY (Data Ready) is an always actively driven output signaling when the conversion is completed and ready to be read out of the device. Data Ready is discussed on page 14 of the ADS1217 datasheet. When the new conversion is ready, DRDY transitions from a high to low state. Prior to that transition is an update period when the new conversion result is placed into the output register. You should not read from the device during this update period.

    If you do not read any data from the device, DRDY will have a low to high transition during the update period followed by a high to low transition signalling the conversion is ready to be read from the device (see the Timing Diagram on page 7 of the datasheet). DRDY will stay low during the conversion period (as no data has been read from the device) until the next update period.

    The description you have described sounds normal for the configuration being used. The action of DRDY is always actively driven so you can determine when a conversion completes regardless of any SPI communication cycle (such as to other devices) and the state of CS.

    Best regards,
    Bob B
  • 0 in reply to Bob Benjamin
    Intellectual 435 points
    Bob:

    Thansk again

    So this really means that DRDYn is always showing the conversion status cycle
    I guess the only way to stop these pulses from DRDYn will be by stoping the main clock CLK (not recommended?)
    Also the DSYNC pin could be used to synchronize these pulses

    Thank you very much

    Fausto
  • 0 in reply to Fausto Bartra1
    TI__Guru** 113765 points
    Hi Fausto,

    DRDY is the method to determine when a conversion has completed and is ready to be read from the ADS1217. This is extremely useful when cycling through the mux and achieving maximum throughput. It is not clear to me why you would want to stop the DRDY functionality. Can you explain why DRDY is an issue for you?

    The DSYNC pin can be used to synchronize or restart a conversion. If you hold DSYNC low the conversions will stop (and DRDY will not change states). If you pull PDWN low, the ADS1217 will power down the internal circuitry and conversions will stop (and DRDY will not change states) until PDWN is placed back high taking the ADS1217 out of power down. Setting the RESET pin low will stop conversions and halt all device activity until RESET is brought back high. Stopping the clock will also halt the conversion, but will also halt any communication.

    Best regards,
    Bob B