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ADS54J42: ADS54J42 temperature issue

HENRY JUNG
Expert 2030 points
Part Number: ADS54J42

Dears.

I am doing the temperature test of ADS54J42.
When the temperature is low and high, system ON / OFF test.
There are two problems.

What is the solution?

1) Room chamber
When it is low temperature(Less than -10 degrees), JESD204B LINK is connected to normal but data is not output.
When the temperature rises(above 5 degrees), it works normally.

2)Sync is not connected at high temperature(above 40 degrees).

The ADS54J42 configuration is shown below.

LMFS : 2242
SYSREF : 5.76Mhz
K : 16
LINE RATE : 3.6864Gbps
lane per link : 2
decimation : x2

BW : 75Mhz

Device Clock : 368.64Mhz

* Register Value

0x0000 0x81

0x0011 0x80

0x0059 0x20 # always write 1 to bit 5 

0x4003 0x00

0x4004 0x68

 0x60f7 0x01 # digital reset : self clearing reset

0x6044 0x00 # digital gain = 6dB

0x6041 0x16 # dec filter mode (bit 5, 2-0), DECFIL EN (bit 4)

0x604d 0x08 # DEC MOD EN (bit 3)

0x6052 0x80 # bus reorder en1 (bit 7)

0x6072 0x08 # bus reorder en2 (bit 3)

0x6000 0x01 # reset digital. Must issue after writes to 6800h

0x6000 0x00 # clear reset

 

0x4003 0x00

0x4004 0x69

 

0x6001 0x32 # SYNC(7), SYNC Register Enable(6), JESD Filter (bit 5-3), JESD Mode (bits 2-0) :"00110010"

0x6000 0x80 # set CTRL K

0x6006 0x0f # set K to 16 (write K-1)

0x6031 0x0a # output lane reorder to get data on DA0 and DA1

0x6032 0x0a # output lane reorder to get data on DA0 and DA1

0x6005 0x00 # 

0x4003 0x00

0x4004 0x6a 

0x6016 0x02 # JESD PLL Mode

  • 0
    TI__Intellectual 1375 points

    For better support, we are in the middle of engaging the best person to support this device. 

    In the mean time, please confirm the followings: 

    • When the link fails,  what is the state of SYNC signal?
    • Please, describe the procedure of the test condition more precisely. 
       1) at what temperature the initial link was established?
       2) When failing at low temp, was the resync tried? Is it successful?
       3) If initial link was established at low temp, do you see the proper data?
       4) From FPGA side, what errors are reported?
    • Does JESD_RX on FPGA have equalization feature?
      What happen if the equalizer is retrained at low temp?

    Regards, 

    Hunsoo

  • 0 in reply to Hunsoo Choo
    TI__Mastermind 18095 points
    We have not heard a response in a bit. I am temporarily closing the post but if there is still an issue please respond with the requested information above and we will address.

    Thanks, RJH