AFE5809: Whether AC coupling required for LVDS Bit clock, Frame clock & Data lines of ADC ( AFE5809 )

Lakshmanan V

Intellectual 480 points

Part Number: AFE5809
Other Parts Discussed in Thread: SN74AUP1T04

Hello sir,

We are using AFE5809 ADC in one of our project.

We are connecting LVDS Frame clock, LVDS bit clock, LVDS data line of AFE5809 ADC to Kintex-7 FPGA.

Whether AC coupling capacitor is required for this LVDS lines ?

Whether SDOUT pin will work at 1.8V logic or 3.3V logic ? We are connecting SDOUT pin to 3.3V logic Bank of FPGA, is that correct ?

We we are attaching the schematic For your reference schematic. Also kindly verify our schematic and let us know if changes made.

AFE5809 SCHEMATIC.pdf

Regards

Lakshmanan V

over 5 years ago

0 Chen Kung over 5 years ago

TI__Genius 12025 points

Hi Lakshmanan,
How are you?
Thanks for using AFE5809 device.
I will look into your SDOUT pin question.

Thank you!
Best regards,
Chen

0 Chen Kung over 5 years ago in reply to Chen Kung

TI__Genius 12025 points

Hi Lakshmanan,

For AFE5809 device's LVDS output circuitry,
please take a look at the data sheet Figure 81. Equivalent Circuits of LVDS Outputs (on page 47).
Its LVDS data directly DC outputs sent to your FPGA (for example).
However, please also take a look on page 17: LVDS OUTPUTS spec:
The Output differential voltage = 400mV
and the Output offset voltage (Common mode voltage) = 1100mV.
These conditions needed to fit (for example) your FPGA device.

The SDOUT output pin follows the data sheet
1) from page 10, Pin Functions table shows The designer can use 1.8-V logic.
2) if needed to change level, from page 49,
8.5.1.2 ADC/VCA Serial Register Readout Description describes:
Level shifter SN74AUP1T04 can be used
to convert 1.8-V logic to 2.5-V/3.3-V logics if needed.

Thank you!

Best regards,
Chen

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AFE5809: Whether AC coupling required for LVDS Bit clock, Frame clock & Data lines of ADC ( AFE5809 )