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DAC38RF84: Verilog/System Verilog simulation model

Part Number: DAC38RF84
Other Parts Discussed in Thread: DAC38J84


I am developing an FPGA design that has to drive the DAC38RF84 through the JESD204B I/F.

It would be useful a Verilog/System Verilog model for RTL simulation during the development phase, ideally something that can  take as input the high speed SERDES lanes and return the sample sent by the JESD transmitter.

I already have the model for the JESD TX including the SERDES lanes.

Is there something available?

Thank you in advance

Best Regards,