Hello team,
I have a couple of questions about external SCLK input for ADS7049-Q1.
The tPH(PL)_CK is required 0.45~0.55tSCLK duty cycle in the Timing Requirements.
1) Is this requirement same through all range of the SCLK rate of 0.016~32MHz?
2) What kind of an issue would be expected if the SCLK was exceeded the max 0.55tSCLK?
3) How comes the max 0.55tSCLK requirement is determined?
As a background of these questions is that to keep 0.45~0.55tSCLK on the clock source may be sometimes difficult, so I'd like to know what would happen in that violated case with considering how marginal this device can cover.
Thanks in advance.
Shinya Sawamoto