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ADS1255: SPI SCLK duty cycle specification

Hisao Uchikoshi
Genius 14300 points
Part Number: ADS1255
Other Parts Discussed in Thread: ADS1257,

Hi Experts,

There is no spec definition for SPI clock duty. Can we understand that we do not care about clock duty and only follow the spec on "TIMING CHARACTERISTICS FOR FIGURE 1"?

P6

Regards,

Uchikoshi

  • 0
    TI__Mastermind 44640 points
    Hi Uchikoshi-san,

    I do not know why we do not have a clock duty cycle specification in the ADS1255 datasheet. I would recommend going by the duty cycle specification given in the ADS1257 datasheet as a more conservative approach, as this is a similar device with the same digital circuitry. In that datasheet we say 40% MIN and 60% MAX.
  • 0 in reply to Christopher Hall
    TI__Genius 14300 points
    Hi Chris,
    Thank you for your answer.
    The spec you were referring to is one for fCLKIN which is the master clock for ADC. We are asking about SPI clock duty. In general, I think that a master clock requires nearly 50% duty due to the stable oscillation. We are expecting that SPI clock is just detecting the rising/falling edge and setup/hold timing and does not matter duty itself.
    Could you please confirm it again?
    Regards,
    Uchikoshi
  • 0 in reply to Hisao Uchikoshi
    TI__Mastermind 44640 points

    Hi Uchikoshi-san,

    Yes I was referring to fCLK, I'm sorry I misunderstood.

    I believe you are correct, if you meet the minimum setup and hold times of the SCLK then it shouldn't be an issue since generally the device only looks at the rising and falling edges of the SCLK signal. To be sure, I will need to check with the design team tomorrow and get back to you.

  • 0 in reply to Christopher Hall
    TI__Mastermind 44640 points

    Hi Uchikoshi-san,

    I discussed this today with a digital designer and our recommendation is to try and keep the duty cycle to min 40% and max 60%.

    In addition to the setup and hold times, there may be some propagation delay between DIN and DOUT which may necessitate the need for some normal duty cycle of SCLK. Most SPI peripherals should provide an SCLK with 50% duty cycle, but if this is not possible (for example in the case that SPI communication is implemented via bit-banging) then the SCLK frequency may need to be reduced. Unfortunately, I do not have any simulation or characterization on this particular parameter to be able to give more specific advise.