ADC08200: voltage source affected by signal generator

Hi Yunkai
One of our ADC experts is reviewing your questions and will respond soon.
Best regards,
Jim B

Hi, my circuit is like this:

The result i get is not stable even if i add buffer between clock and ADC...

Hi Yunkai,

In the schematic you are using, are the decoupling capacitors installed?

Let's go back to the second question in the first post.

"Problem 2: I use signal generator as the clock input. However, the voltage source is affected by the signal generator. maybe 100mV...."

When the clock is supplied, you see the voltage divider (supplying V_RT) sag by 100 mV?

Do you have any signal connected to V_IN? Can you apply a full scale DC voltage ( close to 1.5V), and then apply the clock signal?

Best Regards,

Dan

Hi, Dan

    Really thank you for your reply! This is the circuit i am now testing. I draw it by hand and hopefully you can understand my meaning.

   

The the range is only 0--1.5V in the example giving by the datasheet. I connect to the Vrt to 3V so that the testing range can be 3V.
I connect a DC supply voltage to the Vin. The DC supply voltage range is 0 to 3V. My goal is to verify the function of the ADC. Right now the input voltage is DC voltage, so i think the output bit should be fixed. For example, it the input voltage is 3V, and output 8 bit should be FF(11111111). The input voltage is 1.5V, and the output voltage should be 80(10000000). However, the output bit is not fixed. and this really make the result to a bad situation. Sometimes when the input voltage equals to 0V, the most significant output bit can be 1. And this also happens to the D6 bit. The result is not accurate at all. This will give me very bad result.

Sorry for the misunderstanding and thank you for your reply.

I install every decoupling capacitors. The clock signal is 200Mhz and the clock signal is given by a programmable chip. Another problem is the DC supply voltage is not stable. When i connect the 200Mhz signal to the circuit, the DC supply voltage will have a small voltage interference which has same frequency as clock signal. The DC supply voltage is not fixed since the interference from the clock signal. I think that might be one of the reason why the output bit is not fixed, because the Vrt is changing very second. I tried to use different capacitors and even ferrite beads. But they all can't work. I will post more pictures later! Thanks for your reply again!

Hi Yunkai,

Thank you for thoroughly explaining the issue. I am looking into some things to try and correct your issue.

Can you please lower the V_RT voltage to +1.5V and keep V_RB at 0V (Ground). The datasheet states that the difference between VRT and VRB shouldn't exceed 1.6V. While this might not be the root cause, I just want to make sure that we are in compliance with the datasheet.

Are you able to use a separate supply for DRVDD and AVDD? This should also be done for VRT since you don't want your sampling boundary to be moving. You mentioned that you used ferrite beads, but maybe you could try more inductance between supplies? If the noise is 200 MHz, we can use an LC filter (like 1uH and 10 pF) on the VIN to see if that knocks the ripple out.

Is this being done on a bread board? Another thing to consider would be to use our evaluation board. You can make modifications as needed to fit your design, but it is a good place to start since it is a known working design. ADC08200EVM

Best Regards,

Dan

Hi, Dan

      Thank you for your reply! Now my circuit Vrt=1.5V and Vrb=0V. But i still have some problems.
      When input voltage is still 1.5V. The result looks good. Right now the high voltage for the digital bit is 2.8V. The yellow traces is clock signal.

    Now the input voltage is smaller than 1.5V. The result is not stable at all. The output bit is changing and the yellow traces is also in a weird condition. It is also not stable. 

And when voltage equals to 1.1V. The result is also not good.

But when the input voltage is 0 V, the result is good. All the data is 0 bit. So, that is the reason. The clock signal only stable when the input voltage is 0V/1.5V. That is my problem. Thanks for your reply!

Now the Vdr is still connecting to the Va. I will try to split them later.

Hi Yunkai,

Thanks for providing the scope shots. Here are a few things to consider.

What are you driving VIN with? Probe VIN and share waveform. Even though it is a DC signal, I think it is getting "hammered" by the capacitance of the switching caps. This is an unbuffer input, so I would try adding a small series resistance (like 50 ohms). Does this help? Additionally, you can add a capacitor to ground to create a low pass filter.

Reduce VRT to 1.2V and scale the VIN. Does this still occur?

Best Regards,

Dan