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Original question:

DAC37J82EVM to KC705 simple startup from JESD204B TI reference design

TSW14J10EVM: Design with DAC39J84, TSW14J10 and Xilinx KC705

Star_Li
Prodigy 165 points

Part Number: TSW14J10EVM

My project is using Xilinx FPGA KC705 to do DSP and transmit the processed signal together with I,Q signal by DAC.

I have DAC39J84EVM and TSW14J10EVM. My set up looks like this

Q1: If I use HSDC PRO can I still use DSP or other customized algorithms in my FPGA?
If so, I only find loading the pattern and creating tones functions in HSDC, and I didn't find the part in user guide SLWU087D.

If not, is it do I still need to use the interposer TSW14j10?

Q2: I downloaded Xilinx firmware Source in the TSW14J10EVM product folder, and generated the Vivado project by running a script file. The project has the interface to the JESD204B Core and SDK source code. 

Under which condition do we need to use the source code? As for me, do I need to modify the Vivado project and add my own RTL?

Q3: I need to use DAC to transmit 3 different signals from the lanes, is it possible? In the demo, after loading a pattern file, the signals from different lanes only have a phase shift. I am not sure whether it could transmit 4 completely different signals.

Could you please give me some other suggestion for my project?

Appreciate any help.

Thanks,

Star

  • 0
    TI__Guru* 91947 points

    Star,

    Q1: If I use HSDC PRO can I still use DSP or other customized algorithms in my FPGA? No. This firmware is setup to allow for data transfers from the FPGA to the TSW1410EVM the to and from the PC.

    If not, is it do I still need to use the interposer TSW14j10? Yes. The interposer provides the USB interface between the PC and FPGA.

    Q2: I downloaded Xilinx firmware Source in the TSW14J10EVM product folder, and generated the Vivado project by running a script file. The project has the interface to the JESD204B Core and SDK source code. 

    Under which condition do we need to use the source code? As for me, do I need to modify the Vivado project and add my own RTL? The source code provided a JESD204B interface that would allow you to tap off of it and access the 16 bit parallel data. This code was create by Xilinx using a very old version of Vivado and you will not be able to recompile it with the newer versions without making major changes. You may need to contact Xilinx regarding this.

    Q3: I need to use DAC to transmit 3 different signals from the lanes, is it possible? In the demo, after loading a pattern file, the signals from different lanes only have a phase shift. I am not sure whether it could transmit 4 completely different signals. You can operate this device as 4 individual DAC's, with each one having a different output. Two of the outputs have the P/N signals swapped going to the transformers to make the board routing easier. This might be the shift you are seeing. You can reverse the DAC polarity using the DAC GUI on each of these channels.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 165 points

    Hi Jim,

    Thanks for the reply.

    Q1 follow up: You mentioned the interposer provide an interface between PC and FPGA, but FPGA itself supports usb  jtag  to connect to pc. Since I won”t use HSDC, do I still need to use the interposer card. Will it be helpful  to simplify my design ?

    Q2 follow up: I downloaded the old version of Vivado, compiled the project, load and upgrade the project in the latest version of Vivado. And I can generate bitstream file from the project. My question is what is role of the project and .h .c source codes? My understanding is, with these, I can modify the project, generate my own firmware and setup things through .c files so that I can get rid of HSDC, is it correct?

    Thanks,

    Star

  • 0 in reply to Star_Li
    TI__Guru* 91947 points

    Star,

    If you do not plan on using HSDC Pro, you do not need the TSW14J10. Just plug the DAC directly into the KC705. For your second question, the answer is yes, you can modify these source codes as you like and generate your own firmware.

    Regards,

    Jim