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ADC12DJ3200EVM: TIDA-1021 Sync board External OscIn Option

Apurva Gowda
Prodigy 220 points
Part Number: ADC12DJ3200EVM
Other Parts Discussed in Thread: TIDA-01021, LMK04828, LMX2594, ADC12DJ3200, TSW14J57EVM

Hello,

I'm trying to synchronize two ADC12DJ3200EVM boards using a TIDA-0121 board. I need the boards to be configured as follows:

1)  TIDA-1021 External Oscillator Reference of 10MHz or 100MHz instead of the on-board references.

2) ADC12DJ3200EVM in JMODE0 @4GSPS

3) TIDA-01021 DCLK out at 2GHz.

Is it possible to operate the in the configuration described above? If so, could you provide the changes I would need to make to the configuration files that come with the software?

Thank you,

Apurva

  • 0
    TI__Mastermind 43910 points
    Hello Apurva
    I have contacted the team supporting the TIDA-01021 clocking board to get their assistance.
    We will respond back with more information soon.
    Best regards,
    Jim B
  • 0
    TI__Genius 12550 points

    Hello Apurva,

    Yes, the given configuration should be operable in TIDA-01021 clocking board.

    The External reference clock (10MHz) can be feed at OSCin connectors of the board and clocks will be generated by LMK04828 and LMX2594 for ADC12DJ3200EVMs at JMODE0 and capture cards for synchronization.

    I will work on to generate the configuration files as required and will share with you.

    Thanks!

    Regards,
    Ajeet Pal 

  • 0 in reply to Ajeet Pal
    Prodigy 220 points
    That would be really helpful, thanks Ajeet!
  • 0 in reply to Apurva Gowda
    TI__Genius 12550 points

    Hi Apurva,

    For the given configuration (2000MHz DCLK, 10MHz Oscin) at JMODE0 of ADC12DJ3200EVM, required SYSREF frequency is 10MHz, FPGA Ref clock will be 200MHz with 8GSPS lane rate.

    It requires to change the K value to 10 in "ADC12DJxx00_JMODE0.ini" file in HSDC Pro tool folder.

    Please try the attached .cfg files for programming the LMK04828 and LMX2594 in TIDA-01021 clocking board to generate in-phase clocks with external reference at 10MHz for the operation.

    1021_JMODE0_LMK04828_10MREF_200MFCLK_10MSYSREF.cfg

    1021_JMODE0_LMX2594_A_B_2GCLK_10MREF_10MPFD.cfg

    External reference in requires to remove R45 & R46 and insert R34 & R39 in clocking board.

    It may requires to tune the SYSREF/DCLK delay in LMX2594 to synchronize the two ADC12DJ3200 EVMs. Follow the same procedure as mentioned in TIDA-01021 reference design.

    Let me know, if I can help you more on this design.

    Thanks!

    Regards,
    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 220 points

    Hi Ajeet,

    Thanks for the files. We actually had a TIDA-1021 board printed for us with R34 and R39 populated (R45 & R46 not populated). However, the High Speed Clocking and Data Acquisition software doesn't seem to be recognizing the board because the EEPROM chip hasn't been initialized with and ID. I have posted a separate query on this issue ( see link below). Could you help with this?

    ADC12DJ3200EVM: TIDA-1021: Board not detected by Software: e2e.ti.com/.../2856861

    Thanks,

    Apurva

  • 0 in reply to Apurva Gowda
    TI__Mastermind 43910 points
    Hi Apurva
    I updated the other thread with the FTDI programming information.
    Best regards,
    Jim B
  • 0 in reply to Ajeet Pal
    Prodigy 230 points
    Hi Ajeet.

    Do we also need new .cfg files to replace 1021_ADC12DJxx00_JMODE2_SRC_clear.cgf, 1021_ADC12DJxx00_JMODE2_SRC_EN.cfg, 1021_LMK04828_CLKin0_SYSREF_Direct.cfg, and 1021_LMX2594_A_B_2.7GCLK_33.75MREF_33.75MPFD_SYSREF_OFF.cfg?

    Also, the K value in ADC12DJxx00_JMODE0_trig.ini, are you referring to "JESD IP Core_K"? Currently it is set to 32. Is that what we need to set to 10?

    Thanks,

    Alex
  • 0 in reply to Alex Wargo
    TI__Genius 12550 points

    Hi Alex,

    You can use the existing files except "1021_ADC12DJxx00_JMODE2_SRC_EN.cfg", which is for JMODE2. This .cfg file you need to replace with the attached .cfg file (JMODE0).

    1021_ADC12DJxx00_JMODE0_SRC_EN.cfg

    Yes, If you are using TSW14J57EVM, change the "JESD IP Core_K" value to 10 in "ADC12DJxx00_JMODE0_trig.ini" file (C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J57revE Details\ADC files).

    If using TSW14J56EVM, change the "JESD IP Core_K" value to 10 in "ADC12DJxx00_JMODE0.ini" file (C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J56revD Details/ADC files).

    Thanks!

    Regards,
    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 230 points
    Hi Ajeet,

    Thanks for the help. The boards are now sampling at 4 GHz with a 10 MHz external reference to the TIDA-01021, but there are still some issues.

    After loading the .ini firmware in HSDC Pro to the ADCs, sometimes the ADC will not be able to detect the trigger and timeout. By reloading the .ini multiple times, eventually it will be able to detect the trigger and record data. When the boards do successfully trigger, the captures have inconsistent delay between the boards. It seems that the delay between the boards is -2 ns some times and 8 ns other times.

    Where could this discrete 10 ns of timing inconsistency be coming from?

    Why is the board sometimes not able to detect the trigger after loading the .ini file and is it related to the timing inconsistency?

    Let me know if you need any more info or have any questions.

    Thank you,

    Alex
  • 0 in reply to Alex Wargo
    TI__Genius 12550 points

    Hi Alex,

    Before feeding the clocks from TIDA-01021 clocking board to ADC EVMs, check the clock skew (DCLK-to-DCLK and SYSREF-to-SYSREF) in oscilloscope and use the length matched cables for clock feed as well as clock skew measurement.

    Please follow the HW set up and SW set up (programming sequence) videos for TIDA-01021 mentioned in the below video link, which may resolve the trigger timeout error.

    Get Your Clocks in Sync: Hardware Setup

    Get Your Clocks in Sync: Software Setup

    Regarding the inconsistent delay, it seems trigger is not happening at correct instant or SYSREFs are not align.

    Hope, the above mentioned programming sequence would resolve both the issues.

    Regards,
    Ajeet Pal