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ADS7043: ADS7043 data conversion time clarification required

Nethaji Mano
Prodigy 10 points
Part Number: ADS7043

Hi, 

As per the DS7043 Data sheet, Figure1 timing diagram mentions that the Tconv (conversion time) is 12.5 × tSCLK + tSU_CSCK. 

for eg: in my design if i use 100KHz as sclk, then 12.5*10us+15ns =  125.15us

the conversion data spi shall be available after 125.15 us  T.e after ~13 clocks. 

but in the diagram the Data for sample is mentioned as N during the the conversion time. 

Please confirm the data available in the tconv time is the Data for sample N-1 or Data for the sample N is valid after 2 cycles after the chip select goes low.   

  • 0
    TI__Mastermind 24970 points

    Hello,

    In the Figure 1 image, note that the conversion CYCLE consists of both a conversion period and a acquisition period.

    Let’s take Sample N+1 as the reference, the data clocked out during that CS low period is the data that was acquired during the end of the conversion cycle Sample N. The acquisition time can be as long as you allow it to be, but must be a minimum of 200ns.

    Overall, when CS is brought low, the data clocked out is data just sampled, with no cycle delay.

    Regards, Cynthia