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DAC8802: TIming diagram of DAC8806

Part Number: DAC8802
Other Parts Discussed in Thread: DAC8806, OPA552, THS4011

In the DAC8806 .pdf data sheet on page 13, There is a timing diagram. On the second line from the bottom, there appears to be an alternate timing diagram.  Is that correct?

My understanding is the following:

On can ignore the first three lines where RST=1

WIth LDAC and WR tied together as a single pin (SP)

SP=1     Put data on parallel pins

Toggle SP

After the rising edge of SP the data result is pumped to the analog output.

Is this correct?

Thank you

  • Doug,

    Your understanding is correct. The table is a bit confusing but basically the writer was probably trying to communicate the nature of a single-pin control for WR and LDAC.
  • Duke of DACs,

    I am driving my DAC8806 with an FPGA at 3.3v. Last week a GPIO pin on the FPGA quit working. It is connected directly to pin28(reset) on the DAC8806. I thought nothing of it as the FPGA has gone through a year of testing. I replaced the FPGA and through some more use, the same pin on the FPGA went bad in one day. That run on my PCB goes from pin to pin with no vias.

    My configuration is as follows, I have a THS4011 connected directly to the DAC8806 as per your PDF. The THS4011( at -9v to +9v) then drives a OPA552(-9v to +40v). It all looks good under Tina.

    VREF on the DAC8806 is -9v.

    My goal is to generate what looks like a modified version of the upper part of a 0-30v sine wave or "mountain range". Since I can code 0V, do I really need the reset pin?

    Do you have any idea as to why the DAC8806 kills my GPIO pin? I looked at it with an O-scope. and there is a little jitter at that pin when I turn the system on and off.

    At $100 each for the FPGA, it can get expensive.

    Thanks.

    Regards,

    Doug

  • Answered in a new thread. Closing this one.