Other Parts Discussed in Thread: DAC8806, OPA552, THS4011
In the DAC8806 .pdf data sheet on page 13, There is a timing diagram. On the second line from the bottom, there appears to be an alternate timing diagram. Is that correct?
My understanding is the following:
On can ignore the first three lines where RST=1
WIth LDAC and WR tied together as a single pin (SP)
SP=1 Put data on parallel pins
Toggle SP
After the rising edge of SP the data result is pumped to the analog output.
Is this correct?
Thank you