AFE5801: AFE5801 LVDS pattern read issue

Akshay hublikar

Part Number: AFE5801
Other Parts Discussed in Thread: , DXP

We are using three AFE5801 ICs in our board , All three IC are being fed a single ended clock of 40MHz from FPGA CLOCK pin through buffers.

We are enabling test patterns with SPI writes , and acquiring LVDS outputs with FPGA and displaying them in chip scope tool. We see that the data patterns read are corrupt and not as expected.

But if we reduce clock frquency to 16MHz , the patterns read from LVDS with FPGA chip scope tool looks fine. Data as expected.

Any clue on why at high frequency data is corrupted ?? But we see that clock measured at both 16MHz and 40MHz on a scope looks very similar and less distorted.

over 6 years ago

0 Chen Kung over 6 years ago

TI__Genius 12025 points

Hi Akshay,
How are you?
Thanks for using AFE5801 device.
I will look into your question and will reply to you soon in a couple days.

Thank you!

Best regards,
Chen

0 Chen Kung over 6 years ago in reply to Chen Kung

TI__Genius 12025 points

Hi Akshay,
How are you?
We need to double check on the data sheet from you.
When you read the AFE5801 data sheet's almost very last page
with "REVISION HISTORY".
It mentions:
"Deleted INVERT_CHANNEL and MSB_FIRST rows from register map table"
"Deleted INVERT_CHANNEL register description"
"Deleted MSB_FIRSTL register description"
So please make sure and double check on your register settings.
Please don't use "invert channel" mode
and please don't use "MSB First" mode (Only "LSB First" mode can be used).
And then you should be able to re-run AFE5801 device with higher speed 40MSPS.
Hope this can solve your problem.

Thank you!
Best regards,
Chen

0 Akshay hublikar over 6 years ago in reply to Chen Kung

Intellectual 280 points

Thanks for your inputs .

But we are not using any of these settings , just using

0 Chen Kung over 6 years ago in reply to Akshay hublikar

TI__Genius 12025 points

Hi Akshay,
How are you?
Thanks for letting us know for AFE5801.
Yes, we will look into more details and let you know tomorrow.

Thank you and best regards,
Chen

0 Akshay hublikar over 6 years ago in reply to Chen Kung

Intellectual 280 points

We have done complete Signal integrity from ADC lvds output to FPGA inputs , all looks perfect.

The data sheet we are using doesn't specify anything about the registers you are pointing at.

So need some guidance to resolve this issue.

Above 15MHz clock , data read from lvds is corrupt , below this all looks fine.

We are using altera arria10 FPGA for acquisition

Regards

Akshay

0 Chen Kung over 6 years ago in reply to Akshay hublikar

TI__Genius 12025 points

Hi Akshay,

How are you?
Could you please let us know?
Have you ever used and run our AFE5801EVM plus TSW1400EVM together
with 40MHz Clock Speed?
If yes, then you can compare it with your board design.
Because you can see (from our AFE5801 User Guide) AFE5801 device has been tested
and it worked using AFE5801EVM before.
Please look at the AFE5801 User's Guide at:
www.ti.com/.../afe5801evm
Very important for the board design:
All trace lengths of DxP, DxM, FCLKP, FCLKM, DCLKP, DCLKM all Must be matched
(as the same as AFE5801EVM)
All the register settings must be set (such as Reset the device after power on)
before you set the register Address=0x02

Thank you!

Best regards,
Chen

0 Chen Kung over 6 years ago in reply to Chen Kung

TI__Genius 12025 points

Hi Akshay,

How are you?
If you double check on your board design and board layout
and they are ok, could you pleaser at first, run the following register settings:
(when your both 15MHz and 40MHz input clocks cases):
Address=0x00, Data=0x0001
Address=0x04, Data=0x0008
Address=0x03, Data=0x0000
Address=0x02, Data=0xE000
(please check the output data and see if it is Ramp pattern)

Address=0x02, Data=0xA000
(this output data should be Toggle pattern)

Thank you!

Best regards,
Chen

0 Akshay hublikar over 6 years ago in reply to Chen Kung

Intellectual 280 points

Hi Chen

We are seeing that FCLK and DCLK are distorted at high frequencies , but we have done complete signal integrity analysis upto 400MHz for LVDS outputs , since it is 6 times of input clock

0 Akshay hublikar over 6 years ago in reply to Akshay hublikar

Intellectual 280 points

Hi Chen

Tried all the register settings you mentioned above , did not help , is there any timing adjustments we may have to do on the acquistion side to fix this issue , or this is a hardware issue ?

0 Akshay hublikar over 6 years ago in reply to Chen Kung

Intellectual 280 points

Never used afe5801 evm and tsw1400 evm , but taken good Care to make sure that the design and layout is accurate

0 Chen Kung over 6 years ago in reply to Akshay hublikar

TI__Genius 12025 points

Hi Akshay,

How are you?
From your comment, is it correct that
when you have setup all the registers (as I mentioned above)
and also you have run the RAMP PATTERN mode,
you still cannot capture the correct output data from your FPGA?
And also still it can work on lower speed at 15MHz
but cannot work at 40MHz (higher speed), right?
And also you have checked all the LVDS trace lengths are matched, right?
including both on your AFE5801 board and on your FPGA board together, right?

Then, in this case, could you please to see if you can adjust the timing (delay) from your FPGA?
if possible.
We are running all the AFE5801 test using AFE5801EVM with TSW1400EVM together.
We can run clock at 40MHz (using on-board OSC), all the data captures are working fine.

Thank you!

Best regards,
Chen

0 Chen Kung over 6 years ago in reply to Chen Kung

TI__Genius 12025 points

Hi Akshay,

How are you?

Since you are not using TSW1400EVM to capture output raw data from AFE5801EVM,

and looks like your data capture FPGA is working good when the clock freq is < 15MHz, right?

So could you please double check the following LVDS spec from AFE5801 data sheet spec?

Thank you!

There are some AFE5801 LVDS output specs (very important for stability!):

Please test the output signals (DxP and DxM and Frame Clocks, DCLK Clocks)

their voltage levels (test those pins when they already been connected to FPGA board).

They must follow the above specs:

Output Voltage High =about 1.375V

Output Voltage Low = about 1.024V

And also you need to set your FPGA on those pins as LVDS mode.

And please check your FPGA data sheet, if it can capture the LVDS input signals with the above voltage range spec or not.

Thank you very much!

Best regards,

Chen

0 Akshay hublikar over 6 years ago in reply to Akshay hublikar

Intellectual 280 points

Hi Chen

We are getting most of the patterns perfectly at 40MHz,but only for ramp pattern we see that data is corrupt , any inputs on how to resolve this ?

Regards

Akshay

0 Chen Kung over 6 years ago in reply to Akshay hublikar

TI__Genius 12025 points

Hi Akshay,

How are you?
Great! your system is working at 40MHz now.
Yes, for ramp pattern mode, could you please send me the output signal pattern (picture)?

Thank you!

Best regards,
Chen

0 Akshay hublikar over 6 years ago in reply to Chen Kung

Intellectual 280 points

Hi Chen

Please see attached image

adc1 is perfect

Adc3 is slightly having glitches

Adc2 has lot of glitches

The glitches can vanish with fine tuning of delay ?

Any idea why these glitches are coming ?

0 Chen Kung over 6 years ago in reply to Akshay hublikar

TI__Genius 12025 points

Hi Akshay,

How are you?
Looks like these are due to the unstability issue:
Please check LVDS data output pins with your FPGA data input pins.
and see if data can be sent and be captured at lower freq and at higher freq(40MHz)
and so on.

==================
There are some AFE5801 LVDS output specs (very important for stability!):
Please test the output signals (DxP and DxM and Frame Clocks, DCLK Clocks)

their voltage levels (test those pins when they already been connected to FPGA board).

They must follow the above specs:

Output Voltage High =about 1.375V

Output Voltage Low = about 1.024V

And also you need to set your FPGA on those pins as LVDS mode.
=====================

Thank you!

Best regards,
Chen

0 Chen Kung over 6 years ago in reply to Chen Kung

TI__Genius 12025 points

Hi Akshay,

How are you?
Please also check the timing issue of the output data vs. data capture.

Thank you!

Best regards,
Chen

0 Akshay hublikar over 6 years ago in reply to Chen Kung

Intellectual 280 points

Hi Chen

We have probed adc2 clk and data , data looks stable , also our signal integrity team has confirmed that all 3 ADC layout is exactly same and hence all 3 should behave same .

Our FPGA guy is trying to tune the delay , will update further soon. Hope delay tuning will fix this issue and all data will be clean

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AFE5801: AFE5801 LVDS pattern read issue