ADC08D500: ADC08D500: Interleaving problem

Hi John

I assume your goal is to operate the two ADC08D500 devices in DES mode. Therefore each ADC will be sampling at 1000 MSPS (assuming a 500 MHz clock).

Then you want to interleave 2 devices to enable a total sample rate of 2000 MSPS.

Is that correct?

In that case you will need to skew 500 MHz clock to the second ADC so that it is offset in phase by approximately 90 degrees from the clock to the first ADC. Further fine-tuning of the clock phase will be needed to ensure that the sample instants are offset by 90 degrees due to aperture delay variation between the two ADC devices on the board.

A simpler approach would be to use a device like the ADC083000, This device has a single input, and supports sample rates up to 3000 MSPS, with a clock frequency of 1500 MHz.

This will be a much simpler implementation, and the input bandwidth will be much better (FPBW = 3 GHz) than that using 2 interleaved ADC08D500 devices where each one is operating in DES mode (FPBW = 900 MHz).

I hope this is helpful.

Best regards,

Jim B