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DAC38J84: DAC38J84 AND JESD204B

my lee
Prodigy 20 points
Part Number: DAC38J84
Other Parts Discussed in Thread: DAC39J84

Hello:

At present, The system clock is 156.25Mhz ,  sysref  is 1.953125Mhz,DAC38J84 Can accept 'K' code ,and synchronize .However,when system clock is 160Mhz ,sysref is 2Mhz, DAC38J84 cannot be synchronized.

I wonder which configurations of DAC38j84 need to be modified.

                                                                                                              Thans.

  • 0
    TI__Guru* 79364 points

    Hello, 

    This question is somewhat broad and we can only provide general guidelines. We recommend that you read out the alarms from register 100 to 108 (clear and then read back) for better clarification and narrowing down the issue.

    1. the reference clock to the on-chip PLL (if used) is now changed. Hence, the PLL/VCO tuning code will now need to be changed to ensure PLL is locked.

    2. the serdes PLL will also need to be changed according with appropriate MPY

    3. the SERDES lane rate will now be changed accordingly, the FPGA/ASIC JESD204B lane was not set corresponding to the change.

    4. I am assuming some sort of interpolation is used. if so, the latest data rate * interpolation = final DAC rate exceeded the DAC sample rate limit.

    The list serves only as general debug guidelines.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 20 points
    Hello：
    Thank you very much for your answer, I will explain the details:
    Case 1: The clock is 156.25mhz, 8 LANEs, 8 times interpolation, the output rate of the DAC is 1250mhz, and the registers 100 to 108 have no warning and can work normally.
    Case 2: The clock becomes 160mhz, 8 lanes, 8 times interpolation, the DAC output rate is 1280mhz, and the readback value of registers 100 to 107 is "0703". Indicates "code synchronization error". The FPGA sent the |K| code and the K code received by the DAC is incorrect.
    Note: The PLL is not used in either case and no registers are changed for the DAC. LMFS (8411).
    How can I adjust the registers of the DAC?
  • 0 in reply to my lee
    TI__Guru* 79364 points

    Hello,

    The first issue I see is that the DAC38J84 can only support up to DAC output rate of 1250MHz. To support 1280MHz, you will have to upgrade to DAC39j84.

    The next suggestion I have is to use the DAC38j84 GUI's auto register calculation (setup) to setup the registers needed for case1 and case2. You can then compare the register differences between the two setup. See attached for some example capture.DAC38J84E2E.pptx

    The error you have received also contains FIFO errors. There is a FIFO between the SERDES receiver block (operating at 10bit) and the JESD204B IP (operating at 8bit) inside the DAC38J84. The fact that you have FIFO errors indicates the SERDES input rate is mismatched with the JESD204B rate. Either some of the clock dividers (i.e. register setup) is not correct, or the external SERDES lanes are not set properly. The external serdes lane rate will have to be adjusted on your FPGA. Your SERDES rate have changed from 1562.5Mbps to 1600MBps. It is possible that you have to re-adjust your PLLs and DLLs inside your FPGA design to accomodate the rate change. 

    -Kang