THS1209: THS1209 SYNC Signal problems

user5196208

Part Number: THS1209

I use the THS1209 in two-channel mode via a xilinx spartan6 FPGA.
The problem is that the SYNC signal is not receiving properly.
After initialization by writing 0x401, 0x400, 0x088 and 0x482 to the register, the SYNC signal is fixed to high state as shown below.

However, if the initialization is repeated a few times, the SYNC signal may be output correctly.

And the second problem is that even when the SYNC signal is input, the AD values of the signals coming in AINP and AINM are interchanged.

What am I missing?

over 5 years ago

0 Tom Hendrick over 5 years ago

TI__Guru**** 175481 points

Hi there!

Welcome to our e2e Forum! There are some things you have to keep in mind with the THS1209 - first is that it is a pipeline converter, this means you need to apply the CONV_CLK to get conversions started through the pipeline before you see the first SYNC output. This is described under SYNC on page 14 of the datasheet. Once you get the first SYNC, you need to apply your /CS0, CS1 and /RD in the same manor depicted in Figure 26. If you don't apply the /RD with every clock cycle, you can get some strange behavior from the SYNC output. In the screen shot you provided, you should have started reading data (at least) three/four cycles earlier than what you have shown.

0 Tom Hendrick over 5 years ago in reply to Tom Hendrick

TI__Guru**** 175481 points

Great! You got it working I suppose? No need to initiate multiple configuration writes? That should not be needed.

Do let us know if you run into any more difficulties.

0 user5196208 over 5 years ago in reply to Tom Hendrick

Intellectual 410 points

Thank you very much.
It works properly now

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THS1209: THS1209 SYNC Signal problems