The data sheet SBAS629B –OCTOBER 2015–REVISED JUNE 2017, chapter 7.4.1 says:
To exit RST state, the host controller must pull the RST pin high with CONVST and SCLK held low and CS held
high, as shown in Figure 42. After a delay of td_rst, the device enters ACQ state and the RVS pin goes high.
On the first page of the data sheet, the signals CONVST and CS are connected together.
If the ADC is connected like this, does this mean the device stays in the reset state forever, if the reset pin is pulled low?
Because it's not possible any more to put CONVST low and CS high to leave the reset state.
Thanks for any feedback
