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ADS41B49: No output clock and no SPI readback

Jakob Harmon
Prodigy 30 points
Part Number: ADS41B49

We are in the DVT process with a new board and are not able to get a high-speed differential clock output nor a SPI readback from the ADS41B49.

1. Output clock issue: We have a 192 MHz differential clock present at CLKP/M as driven by an FPGA, and verified on a scope.  However the 192 MHz output differential clock isn’t being generated and output on CLKOUTP/N as verified on a scope.

2. SPI issue: SPI commands are coming from an ARM processor and verified on a scope to look correct.  The ADC isn’t responding to SPI read-back commands, when theoretically it’s been put in READBACK mode.

To resolve both, we've tried initial HW reset on the RESET pin, as well as, a SW reset through the SPI interface.  Neither makes a difference.  All voltages and grounds to the chip appear correct.  Please assist in resolving these issues.

  • 0
    TI__Genius 12780 points
    Hi Jakob,

    One of our device experts is reviewing this issue, and will return with you shortly.

    Best Regards,

    Dan
  • 0
    TI__Guru* 91947 points

    Jakob,

    A sample clock is not required for the SPI to work so lets focus on getting the SPI working first. How fast is the SCLK on your interface? Do you have RESET tied low? Do you have DFS tied high? Is OE high or disconnected? Is pin 23 open?

    One SPI test to try that does not involve the read back is to monitor power while placing the part in power down mode. If the SPI write is working properly you should see a reduction in current. Once you do get the SPI working, you must reset the ADC using a SPI command first or pulsing the RESET pin from a low to a high then low again.

    Regards,

    Jim 

  • 0 in reply to jim s
    Prodigy 30 points
    The SCLK is running at 3MHz. We send an initial pulse to RESET, then it is tied low. We have DFS tied low to get twos complement, DDR LVDS on the data interface. OE is currently tied low by an FPGA (I'm seeing now this is why there is probably no output clock). Pin 23 is open.
  • 0 in reply to Jakob Harmon
    TI__Guru* 91947 points

    Jakob,

    Are you following the procedure below from the data sheet regarding register read options? Is your FPGA capable of reading 1.8V logic level for this pin? Did you try the power down test I mentioned?

    Regards,

    Jim

     

    After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When

    the readout mode is enabled, OVR_SDOUT outputs the contents of the selected register serially:

    1. Set the READOUT register bit to 1. This setting puts the device in serial readout mode and disables any

    further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is

    also located in register 0. The device can exit readout mode by writing READOUT = 0. Only the contents of

    the register at address 0 cannot be read in the register readout mode.

  • 0 in reply to jim s
    Prodigy 30 points

    Jim,

    All reported issues are resolved.  Setting the OE pin to high enabled the output data and clock from the ADC.  Secondly, we've realized the SDout pin is not tied back to the ARM interface, hence we can't read back data from the ADC.  However, we have verified that the registers are being written correctly using the power down test you mentioned.  Additionally, we have put the ADC into test mode and seen the digital ramp and the 10101010101010 outputs inside the FPGA.

    Jake