Other Parts Discussed in Thread: DAC38RF82, LMK04816,
Hi!
I am using the DAC38RF89. DACCLK frequency is 328 MHz, DAC clock frequency is 7872 MHz.
There is a problem when I 'm trying to implement Figure 141 (refer to DAC38RF82 datasheet, p.126):
On "Chip PLL Mode" stage, readed data from <page 0, address 0x06> always the same and never change - 0xc002.
When configuring DAC power consamption increases about 1 W.
Can you give me an advice?
Thanks.