ADC3441: Input clock jitter tradeoffs

Ben van den Bergh

Intellectual 435 points

Part Number: ADC3441

Dear forum members.

Could you please comment on the following?

Background:

We intend to use a ADS3441 in a new application at 25 MSPS.

The clock will be LVDS at 10MHz (CLKP-CLKM), frequency could be changed if needs be.

Question:

If we want to achieve the full SFDR of the ADS3441 what would the ideal and worst case clock jitter have to be given the abovementioned parameters.

The graph on page51 of the datasheet (Figure 151) unfortunately does not provide much detail at lower bandwidths

The datasheet does however state a typical clock jitter aperture of 130 fs rms.

Thank you

over 5 years ago

0 dBrock over 5 years ago

TI__Genius 12780 points

Hi Ben,

The clock jitter, ideally, will not impact the spurious performance of the ADC, so SFDR should remain stable, but SNR will primarily impacted.

This figure on page 51 is showing the effects of the ADC aperture jitter on increasing input frequencies (Fin). Ideally, you would want to have a clock source with jitter that is lower than that of the ADC (~130 fs), as to minimize the external jitter into the system.

The higher the input frequency is, the greater the effect jitter has on the SNR. This table illustrates the impact of aperture jitter in relation to input frequency.