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ADC12DJ3200: About TIDA-01028

Part Number: ADC12DJ3200
Other Parts Discussed in Thread: TIDA-01028, TIDA-01022, TEST, ADC12DJ5200RF

Hi,

   I am planning  to design a 20GSPS high speed osciloscope using 4 interleaving ADC12DJ3200. In TIDA-01028 user guide,Figures 31 and 32 show the ADC performance with IL spur and without IL spur.I hope to achieve the performance of Figure 32.Here I have two questions:

  (1)  what calibration has been performed to remove the IL spur?

  (2) Does calibration  need to be done only once, or do it need to be calibrated every power on cycles?

Thanks a lot!

  • Hi ldx
    I have notified the TIDA-01028 experts regarding your question. Someone should provide a more detailed response soon.
    Best regards,
    Jim B
  • Hi ldx,

    Figure 32 shows by removing IL spur what best performance can be achieved. Typically customer will do their own off line calibration method to reduce IL spur.

    How we can reduce on chip IL spur
    (1) what calibration has been performed to remove the IL spur?
    a) Fore ground / back ground helps to reduce offset and gain error
    b) tAD adjust feature of ADC12DJ3200 helps to reduce Time mismatch

    (2) Does calibration need to be done only once, or do it need to be calibrated every power on cycles?
    It should be done every power cycle and monitor temperature , voltage variation then calibrate to get better performance.

    Let me know if you have any further questions.
  • Hi ldx,

    Could you please share additional information to understand better your requirements

    1. ENOB requirement
    2. Input BW, SNR , SFDR
    3. Is it typical scope architecture , 4 channel , 2 channel and 1 channel operation ?
  • Hi,
    Thanks for your reply.
    The requirements are as follows,
    1) Input signal frequency range is DC-8GHz,
    2) SNR is better than 40dBFS, SFDR is better than 45dBFS.
    3) This oscilloscope supports 4 channels.

    I am ready to calibrate using the following methods:
    When powering on, the offset error and gain error are obtained by calculating the mean and root mean square values respectively using a 100MHz calibration signal.The phase offset between channels is obtained by FFT or mutual correlation. For temperature changes, we are prepared to keep a temperature coefficient lookup table in EEPROM for offset,gain and phase skew.Then we use the offset gain error to compensate the sampled data,and use the phase skew to adjust ADC tAD settings to achieve inter-channel consistency.
    These methods are based on the difference between channels that are frequency independent. If the difference between channels is related to frequency, the entire frequency range needs to be calibrated.It needs to be calibrated with a series of frequency signals.
    According to your experience, do you think there is such a situation that the difference between channels are frequency dependent? In addition, for the calibration steps mentioned above, please please give some advice..
  • Hi ldx,

     

    Thanks for the information 

    1. Yes , you have to use serious of frequencies for calibration since we can see not linear behavior in clock skew and jitter going higher frequency.
    2. Also apart from analog front end , the clock path delays to be well matched to reduce IL spur effects
    3. We are also planning to do separate reference design based on TIDA-01022 platform which talk about calibration schemes / techniques       that help to optimize system performance. We would like to hear from your system design challenges and associated key care spec . 
    4. Calibration steps seems ok and will provide some more feedback after discussing with our other systems experts.

    Also this 4 channels scope will operate 4 ch- each channel sampling at  6.4GSPS, 2 ch - 12.8 GSPS and 1 ch- 25.6 GSPS right ? 

  • Hi,

    Thanks for your quick reply.

    1.  Yes,this 4 channel scope will operate 4 ch- each channel sampling at 6.4GSPS, 2 ch - 12.8 GSPS and 1 ch- 25.6 GSPS .

    2 . I am waiting for your new reference design based on TIDA-01022.

    3   If the gain mismatch and phase skew between channels are related to frequency, it is necessary to calibrate with a series of frequencies, obtain a series of calibration coefficients, and use different calibration                   coefficients at different input frequencies.

         For input signals of any frequency, especially those with very wide bandwidth, I think a filter should be used to calibrate the sampled data. Then we need to consider how to design this filter. And the useful bandwidth        of the filter may be less than FS/2. In order to achieve 8GHz bandwidth, we may have to use a higher sampling rate, such as 20GSPS.

         Can you give some suggestions about these ideas mentioned above?

  • Hi,
    These days I have considered that if these errors are related to frequency, it should be impossible to compensate each channel with a digital filter. It is only when the signal frequency is less than half of the single-channel sampling rate that each channel can be compensated by digital filtering.So it seems that the only hope is that the error between channels is independent of the input frequency.
  • Hi Ldx,

    let me know what kind of filter you plan to use compensate error ? can you give some idea about that.

    If you take clock jitter alone impact SNR at higher input frequency.

  • Hi,

    Suppose there are 4 channels A,B,C,D. First, we measure the and amplitude and phase difference of the channel B,C,D relative to channel A at a certain frequency interval over the entire frequency range. Then a time-domain digital filter is designed to compensate for the difference of amplitude and the phase characteristic relative to channel A. When the sampling signals of the channel B,C,D pass through their respective filters, they will have the same amplitude and phase characteristics as channel A.

    According to your test, what is the range of channel timing skew between channels within the 0-8GHz frequency range?I want to know the performance(SNR, SFDR) in the 0-8GHz range is if it is calibrated with only one frequency point, such as 1000MHz?
  • Hi,
    It seems that time interleaved ADC can improve sampling rate, but it is of little use to increase signal bandwidth.
  • Hi Ldx,

    Yes, but it depends on ADC input bandwidth support. if we operate ADC12DJ3200 in single channel mode max sample rate is 6.4 Gsps and it requires 3.2 GHz instantaneous input bandwidth but ADC12DJ3200 can support max 8 GHz input bandwidth. if we interleave 2x,4x we can use 8 GHz full bandwidth of ADC12DJ3200.
  • Hi
    I am ready to design an oscilloscope using 4 ADC12DJ3200 with 20GSPS sampling rate and 8GHz instantaneous bandwidth. My idea is to minimize group delay ripple and insertion loss at the front end of the ADC, and ensure coherence between channels.


    Do you think this specification of 8GHz instantaneous bandwidth is achievable? Can you give some advice on hardware design?
  • Yes, you can refer TIDA-01028 hardware platform for startup.
    One more option you can consider ADC12DJ5200RF , we recently released 5.2 Gsps dual channel , 10.4Gsps single channel ADC. By interleaving x2 devices you can get 20.8Gsps.
  • Hi
    Thanks for your quick reply.
    The problem I've been confused about these days is that if the channel difference is related to frequency, then we can't compensate for the difference between channels over the entire frequency range with the same parameters. This makes it impossible to measure the wideband signal . Do you think so?