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ADS54J20EVM: SR#1-4595481663, PN:4265900004

Part Number: ADS54J20EVM
Other Parts Discussed in Thread: ADS54J20,

When using FPGA to configure the register of ADS54J20, SPI timing sequence was normal, SCK frequency was 1MHz, register readback was normal when configuring analog Bank, SPI cannot read back when configuring JESD Bank. it seems that the SPI link is OK. the analog bank is working properly. 


Is there anyother hardware issues caused this error ?  different power supply ? or anyother configuration  error?

thank you and looking forward to your reply ASAP.

  • Peng,

    You must first write a "1" to bit 0 of address 0x00 in the main digital page 0x6800. After loading all of the other values in this page, you must then pulse bit 1 from 0>1>0 of address 0xF7 in the same page. Also make sure the device clock and SYSREF are running. See attached example from the EVM GUI.

    Regards,

    Jim

    ADS54J20_2x_dec_lowpass_4222.cfg

  • Hi Jim,

    Thank you for clarification.

    The clock and SYSREF signal are not runing in this case . the PLL moudle is not enabled.

    the JESD bank could not be read without those signals?
    thanks.

    BR//
    Peng
  • Peng,

    These clocks are needed for the SPI state machine. Try you test with these present.

    Regards,

    Jim

  • Hi Jim,

    thanks for your great help. Problem have been solved.

    One more question ,  the PLL module enabled(up to 1G clock ), and the JESD bank working normal.  can I think that the output of the PLL module , clock and sysref is generally OK, as functionally.

    I haven't done the test of the PLL module yet.

    thanks a lot.

    BR//

    Peng

  • Peng,

    Glad to hear this. Can you explain a little more about your PLL module question? I am not sure what you are asking for. Are you referring to the device providing the clock and SYSREF to the ADC? 

    Regards,

    Jim

  • Hi Jim,
    The PLL module configuration refer to the EVM board file. The PLL moudle enabled and the JESD bank is working normal. So far,there is no problem and I just want to know whether my PLL module is providing the correct SYSREF and CLOCK that the SPI could be work normal or the SPI works as long as there is clock and SYSREF data input. Next comes system debugging, there must be more problems.hoping to your great suooprt ,thank you very much.

    BR//
    Peng
  • Peng,

    Are you using the TI ADS54J20EVM with your FPGA board? If so, the configuration files that the GUI loads into the on-board LMK allows the device to provide the proper device clock and SYSREF signals after the file is loaded. You can use these configurations files to help you with sending the proper register data with you SPI interface. The GUI has configuration files for both the ADC and LMK. You must always first program the LMK first, reset the ADC, then program the ADC. Otherwise, the SPI will not work.  

    Regards,

    Jim