Hello, I am looking at using the DAC2900 for an application we have here, and I want to use it in a very specific way, that I believe the timing diagram on page 5 allows my use case but I'd like this confirmed:
I do NOT want to tie the write and clock signals together. I am driving from an FPGA so I have full control of my data and control input signals. What I want to do is latch the data as shown in the timing diagram, then not do the second rising clock edge until a time in the future that I specify, maybe microseconds later. So I will not be providing a symm
etric clock or write signal, but I want to use them more as true latch signals.
The timing diagram does not call out a low pulse width, so I believe that if I follow the tlpw, tcpw, tcw then I will be able to do what I want. Is this true? Can I provide an asymmetric clock signal?
