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ADS1246: vbias intermittently connected to AIN0?

Part Number: ADS1246

Hello,

This thread is in the continuity of :

https://e2e.ti.com/support/data-converters/f/73/t/741611

and

https://e2e.ti.com/support/data-converters/f/73/t/753350

Even after we changed our Vref voltage from 3V to 1.8V, we are still facing a strange artifact on our measurement, the one that initiated this investigation and redo of our schematic.

Changing Vref to a lower voltage did a good job, but did not remove the initial problem.

But today, I can reproduce the effect, without understanding the cause.

It seems that time to time, vbias is connected to our sensor output via trough AIN0.

I am pretty sure that it is this voltage, because for the last few years, the impacts are exactly the same in our records as if I use VBIAS_reg_01h with 0b00000001 => bias voltage is applied to AINP

We suspected a SPI glitch, but working with registers didn't seems to work. The thing is that I have to recording period between which I am able to remove the artifact :

1 - The problem is present in our measurement.

2 - ADCs are reset and VBIAS register written to 0x00, read and checked to be 0x00  ,problem still here

3 - 3V ana and 1.8V ref off

4 - 3V ana and 1.8V ref on

5 - ADCs are reset and VBIAS register written to 0x00, read and checked to be 0x00  ,problem disappears.

It seems that when "vbias leaks" (I use quotes as I would like to check with TI), the only way to stop it is to turn off analog supply as resetting register doesn't seems to be effective.

By writing VBIAS _reg_01h, I can reproduce or remove our artifact. But when this appears when it wasn't intend for, registers are not effective and action on power supplies are required.

Do you have knowledge of unwanted vbias connection in the multiplexer circuit §9.3.1 of the data-sheet?

If not, we struggle to understand why when our artifact problem appears, the only way to get things go normal again is to power the ADCs analog off as a numerical reset only doesn't seems to work.

hints and help would be greatly appreciated.

  • Hi Quentin,

    You have some interesting observations regarding VBIAS.  However, this may not be caused by SPI commands directly.  This could be caused by a transient.

    A couple of things your schematic snippet doesn't show is input filtering on either the reference input or the analog inputs.  It is very possible that a transient event occurred and without adequate input protection and filtering there could be an issue.

    I'm not quite sure what you meant by 'numerical reset'.  Does this mean sending the SPI RESET command?  Or does this mean you toggled the RESET pin?  Toggling the RESET pin should have the same effect as powering off/on AVDD.

    It would be extremely helpful to see the entire schematic.  You can safely send me the schematic to TI by using the following email address:

    mailto:pa_deltasigma_apps@ti.com

    Best regards,

    Bob B

  • Hello,

    We have direct connection without bypass for input as shown in our schematics.
    When we reset the ADCs, we begin by toggling the RESET pin and after, we send the reset command, wait 0.6ms and write registers for configuration.
    I am sending you the full schematics
  • This discussion has been taken offline.

    Best regards,
    Bob B