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AFE7225EVM: AFE7225EVM - Putting ADC/DAC chain into loopback mode to test 'Analog In / Analog Out'

Part Number: AFE7225EVM
Other Parts Discussed in Thread: AFE7225


I am currently working with the AFE7225 EVM and am trying to put the device into 'RX-TX loopback' mode so that I can inject an analog signal into the INA+ (J3) SMA Connector and look at the signal output on the 'IOUTA' (J5) SMA connector to just verify that the IC itself is working as expected. I have modified the EVM to bypass the U2 CDC IC and am feeding in two single-ended clocks into the CLKINP / CLKINN SMA connectors (J18 / J19) to try to streamline the setup. I also tried to bypass the entire TX/RX processing chain so it was as simple as possible.

The board modifications are as follows:

1) Install R112, R74 and remove R76 (per note in EVM guide, pg 13, section 6.4)

2) Install SMA connection into J19 and install R161

3) Remove T9 transformer and bridge pins 3 - 4 so that the CLKINP signal goes straight to C51

4) Remove R78 and R81

Once these mods were done, I have confirmed that I have good clocks (with the appropriate levels) at IC pins # 8 & 9 (CLKINP = ADC_CLK and CLKINN = DAC_CLK per datasheet, pg. 45)

Register Settings:

(all registers set from EVM GUI, version 1.3)

'0x20' written to address '0x20A'    (Single Ended Clock mode setup)

'0x03' written to address '0x105'    (RX_TX_LPBK Mode)

'0x60' written to address '0x103'    (TX_Byp)

'0x60' written to address '0x167'    (RX_Byp)

If I switch the 'TX_Byp' off, I can get the 'built-in' DAC test loop registers to out a pattern so that seems to imply that have a good DAC clock chain however, there is a note on pg 22 of the datasheet that states that in loopback mode, 'it is still required to give an active DAC_DCLKIN because the TX FIFO requires it for proper data transfer'. This is somewhat confusing to me and seems to imply that I still need to inject a signal on the 'DAC_DCLKIN' via the J21 SMA connector (after install R94 / R95 and removing R64 / R93) which I have tried, but to no avail.

Can anyone please provide some insight as to how to get the EVM module running in the 'RX-TX' loopback mode?


Chris Laatsch

  • Chris,

    We are looking into this.



  • Hey Chris,

    As a quick sanity check, can you make sure that all of the clock signals sources you are using for CLKP, CLKN, DAC_CLKIN are coherent & tied to the same reference. Also, are you using two different clock sources for CLKP & CLKN. Typically we recommend that you use one clock source connected to an external balun to produce a differential clocks before connecting them to the EVM. If these quick tips don't fit the bill i would actually recommend that you first confirm that you can perform a single-tone capture as well as send a tone through HSDC pro to the AFE74xx using your setup.

    Have you been able to do that already?

    I would do this because you have made quite a few modifications to the board & taking a step back can help isolate whether the ADC or the DAC or both is the issue. After verifying a capture & transmission of a signal, setting the EVM in loopback mode should be easy.

    While you're at it can you please let me know what the clock rate is that you are sending to CLKP & CLKN, as well as the interpolation factor, desired DAC clock rate and ADC clock rate. If you're able to, please send me a copy of the configuration file that you are loading to the GUI.