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DAC37J84: SPI state when powered down

Part Number: DAC37J84

I've asked this question before but the response was locked before I could ask for clarification.

Original questions:

When the device is powered down, what's the state of the SPI bus? Does the device pull it low? I have it sharing the bus with other devices. I'd like to turn the device off when not used to conserve power, but will this make the SPI bus not accessible to other devices on the bus?

Additional:

What happens when you power the device down? Does it pull the SPI bus low? In our current design we have multiple devices on the SPI bus. But we want to be able to turn some devices off and others on. However, when power down the DAC it seems to pull the SDO down. 

Do I lose the SPI bus when the DAC is powered down? Is this expected behaviour? 

  • Patryk,

    I must have misunderstood your question in the beginning. 

    The answer regarding SPI bus during power down is that it will be an unknown state and we cannot guarantee the functionality. The SDO output pin is a basic CMOS inverter with tri-state capability. The tri-state signal is driven by internal SPI logic such that during  input condition (register write), the SDO bus is tri-stated. The upper PMOS of the inverter is driven with a logic hI to turn off the PMOS of the tri-state logic (you may do a web search on the tri-state function with CMOS inverter to understand the circuit analysis).

    In power down mode, we cannot guarantee the SPI logic whether it sends logic HI or logic low to the tri-state of the SDO. It is unknown because it is in power down.

    I recommend you keep the device in powered mode (i.e. voltage applied to all the device), and simply set the the sleep mode registers to be enabled to achieve the mode 10 deep sleep mode power consumption (see datasheet page 10)

    -Kang

  • Thanks Kang, that makes sense.