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ADC12DJ3200: different regulators for LMK04828 and LMX2582 and review for clocking scheme

Part Number: ADC12DJ3200
Other Parts Discussed in Thread: LMK04828, LMX2582, TIDA-01028, , LMK04828-EP, LMK04832

Hi TI,

We are using three ADC12DJ3200 in our design.

In eval board for ADC12DJ3200, separate LDOs are used for LMK04828 and LMX2582.

But in TI TIDA-01028, in which two ADC12DJ3200 are used, single regulator is used for both LMK04828 and LMX2582 although power rails are separated using ferrite beads.

In our design ,we are also using HMC987  buffer from ADI for clocking ADCs. 

Below is the clcoking scheme:

 CLOCKING.pdf

So our questions are:

1. Will there be any issue if we use single regulator for LMK04828, LMX2582 and HMC987? What does TI recommends?

2. What are TI thoughts about our clocking scheme?

Thanks,

Lalit

  • Lalit,

    We are looking into this.

    Regards,

    Jim

  • Hi Lalit
    I need a little more time to review the HMC987 details and requirements. I should have a response tomorrow.
    Best regards,
    Jim B
  • Hi Jim,
    Any update on the above two questions asked?

    Thanks,
    Lalit
  • Hi Lalit
    For Q2:
    It looks like your clock architecture involves passing a 100 MHz reference through the LMK04828 PLL1 for jitter cleaning and using the OSCOUT (also at 100 MHz?) as the reference clock for the LMX2582. Is that correct? In that case I would also recommend using LMX2582 RFoutB as an input clock to the LMK04828 Feedback CLKin so it will be used to generate the SYSREF clocks and FPGA clocks (not shown in your diagram). This is the configuration used in the ADC12DJ3200EVM to give good flexibility of ADC clock frequency based on a 100 MHz reference VCXO (Y1).
    For Q1:
    To get the best jitter performance from the LMK04828 and LMX2582 PLLs I would use separate linear regulators for each clock device.
    If you choose to use a single regulator it will be very important to use good series filter components and decoupling capacitor arrays to isolate the noisier devices from impacting the LMX2582 and PLL1 of the LMK04828. You will also need a regulator with higher output current capability than the TPS7A4700 devices used in the ADC12DJ3200EVM.
    Best regards,
    Jim B
  • Hi Jim,
    Thanks for your inputs.

    For Q2:
    If we use the below scheme for clocking , do we still need to provide LMX2582 clock output to LMK clock inputs?

    For device clock to ADCs :

    Refclk_100Mhz----> LMK04828_FBCLKIN pin ----> DCLKOUT1-----> LMX_OSCin pin------->LMX_CHA_OUT---> HMC_CLKin----->HMC_OUT----> ADCs_CLKin

    Sysref for ADCs and Clocks for FPGA will be provided by LMK04828.

    Please give your inputs on that.

    Thanks,
    Lalit
  • Hi Lalit

    That architecture requires PLL2 of the LMK04828 to be used to create an internal RF clock which is divided down to generate the DCLKoutx and SDCLKoutx outputs. The PLL2 VCOs can only create clocks in the following frequency ranges,

    VCO0 2370 MHz to 2630 MHz

    VCO1 2920 MHz to 3080 MHz

    These frequencies may limit the available FPGA DCLK and system SYSREF clock frequencies that can be generated and will therefore limit the ADC clock frequency that can be used. Using PLL2 to generate the RF clock for distribution may also result in larger variation in skew between the CLK and SYSREF signals going to the ADC. This variation can be due to system/IC temperature or supply voltage shifts.

    The architecture I described provides more flexibility of system clock frequencies and lower skew variation. This diagram shows the basic architecture and the options present on the ADC12DJ3200EVM:

    ADC12DJxx00EVM Clocking A.pdf

    Best regards,

    Jim B

  • Hi Jim,
    I have checked the datasheet of LMK04828.
    According to datasheet , the maximum input clock frequency for feedback clock pins is 3.1Ghz, but LMX2582 will give 3.2Ghz .
    So how can we connect channel B output of LMX2582 to LMK04828?

    Thanks,
    Lalit
  • Hi Lalit
    The LMK04828-EP and LMK04832 devices can accept input clocks at up to 3200 MHz.
    The LMK04828-EP is pin and function/register compatible with the LMK04828. The LMK04832 is similar, but has some pinout and function/register differences.
    Best regards,
    Jim B
  • Hi Jim,
    Is there any other differences between LMK0482-EP and LMK04828 other than maximum input clock frequency for feedback pins?
    Also 3200 Mhz is the maximum input frequency for LMK04828-EP.
    Is it okay to operate LMK04828-EP at its maximum input clock frequency? Will it not affect LMK04828-EP performance?

    Thanks,
    Lalit

  • Hi Lalit
    The LMK04828-EP has a wider allowed ambient operating temperature range. I think a number of other specifications are also changed. It would be best to ask a new E2E question on that topic to ensure the clocking and timing experts responsible for those devices provide their answers.
    The LMK04828-EP will work well in distribution mode with 3200 MHz input and lower frequency outputs. In this application the outputs of the LMK04828 are the FPGA clocks and the SYSREF for the ADCs and the FPGAs. All of those clocks have less stringent jitter requirements than the ADC clock which comes from the LMX2582 and HMC987 buffer.
    Best regards,
    Jim B