AMC1210: Modulator Failure Interrupt Not Working

Hi Ben,

Thanks for your post! My thinking is that since the clock is being removed completely as opposed to slowed down, the device cannot determine that the MCLK clock is less than 1/64th of the system CLK as the equation is un-resolvable without a full clock period.

Have you tried testing this with a signal generator to confirm that the flag is being set correctly when the clock period is manually slowed down?

Hi Alex,

Thanks for the reply.

I tried your suggestion with connecting a signal generator to the CLKx input.

I have input a square wave signal into the CLKx pin with a frequency of 1.4 MHz (which is slower than 1/64th of the system CLK (1.406MHz) ).

Doing this did not cause the interrupt to trigger.

I also tried increasing the frequency from the signal generator to 10 MHz, then decreasing it back to 1 MHz, which also did not cause the interrupt to trigger.

Kind Regards,

Ben Gittins

Hi Ben,

Thanks for giving that a try. Give me a few days so I can get into the lab and take a look on my side. I'll try to have an answer for you by the end of the week.

Hi Ben,

Sorry for the delay. Still working on this one, testing is in progress.

Hi Ben,

Any update on your side?
I've found that the data collection routine for the sample program I'm trying to debug this with has some built in functions that are giving me trouble. Perhaps my observations will help.

1. The data gather function pauses until the clock returns. I'm able to see in the bit stream where the data is corrupted when the clock line is removed, however data collection stops (instead of continuing to run, resulting in a lock up) and does not attempt to continue data collection until the clock is back.
2. An additional function causes the modulator failure flag to be instantly reset before I can see it toggle.

Hi Alex,

No updates from my side.

I'm guessing this sample program is one that is run on the AMC1210 chip?
Is it similar to the software on the AMC1210 chip that I am using?
If so, then if the modulator failure flag is set, shouldn't it only reset after the interrupt register is read (assuming that the modulator stops failing before the interrupt register is read)?

Also, may I ask if you tried reproducing the same observations that I had (the lack of a clock signal not triggering the modulator failure interrupt, the 1.4 MHz signal not triggering the modulator failure interrupt)?
If you get different results, then maybe the way that I performed my test may have been incorrect.
If you observe the same results that I have, then I would be curious to know what conditions are required in order for the modulator failure flag to be triggered.

Kind Regards,
Ben Gittins

Hi Ben,

The AMC1210 is just a SDFM, so it has firmware, but not software - the software is loaded/ran from an MCU. Are you using the AMC1210EVM GUI to debug this? If so, how are you checking that the flag has been set?

I'm using a C2k with a data collection program to read from my AMC1210EVM.

I tried reproducing the error that you originally asked (missing CLK line), but I have not tried slowing the clock down yet.

Hi Alex,

I am not using the AMC1210EVM. I am using a board of our own design.

Using an Infineon XC886 on our own board, I check whether the modulator failure flag has been set or not by reading the interrupt register directly via SPI. I do this independently of whether the INT signal from the AMC1210 has been triggered.

Kind Regards,
Ben Gittins

Hi Ben,

Still working on this one with mixed progress - we're consulting the C2k team for additional help with our code.  

Hi Alex,

I'm just wondering if you have made any progress with this at all?

Kind Regards,

Ben Gittins

Hi Ben,

Unfortunately not. I haven't been able to get it to trigger reliably without immediately being cleared. 

Hi Alex,

Do you know why it is not triggering without immediately being cleared? Is it due to the software you are using? Or is it due to the way the chip itself is function?

Also may I ask the conditions you have to trigger it in the first place?

Kind Regards,

Ben Gittins

Hi Ben,

It's due to the software I'm using - it was written to perform a certain function and "reset" if something wasn't right, like when the clock is missing. 

Just removing the CLKx line like the test you're trying to perform. 

Since I'm not having much luck with editing the code, I've gone through your register settings again and have a few things I'd like you to try/confirm.

Just confirming that your master CLK line is coming from the MCU? If possible, can you provide a schematic? If you're not comfortable sharing on the forum let me know and I can send you and email offline. 

Can you read the register values back to confirm they're being written correctly?

Confirming that the channel register settings are being written to multiple locations since each channel has a separate register. 

Try enabling the acknowledge flag. Change Sinc Filter Register from 0x0DFF to 0x0FFF. Can you see this flag toggle as data comes in?

Is everything else setup before setting MFE to high? Clock Divider Reg: 0x0800

Hi Alex,

Sorry for the long delay.

I won't be able to provide a schematic, however I can let you know that the signal on the CLK line of the AMC1210 is supplied by a 32 MHz clock oscillator chip.

The register values I gave to you initially were confirmed by reading back from the registers.

I have also previously seen the acknowledge flag toggle as data comes in.

The Clock Divider Register is the last register I configure, with the MFE set to high.

Kind Regards,

Ben Gittins