ADS42JB69EVM: ADS42JB69EVM not sending sync codes when sync is driven low.

Kate Rayhman

Prodigy 40 points

Part Number: ADS42JB69EVM
Other Parts Discussed in Thread: ADS42JB69

Hello,

I have a ADS42JB69EVM connected to KCU105 through the FMC connector.

I'm having a problem recieving sync codes when the FPGA drives the sync low.

Afetr power up, I load the .cfg file throu the TI EVM GUI and configure the Xilinx JESD204 IP.

I can see the sync driven low but the code is not received.

The interesting part is that if I change (in tab ADS42JBXX) "SYNC Request" from "Normal Operation" to

"Generate SYNC Req", I can see the right codes on all the lanes, so I don't believe it's a connection problem.

I can also send it successfully through "Link Layer Test Mode".

I will appreciate any guidance to resolve it.

Thank you,

Kate

over 4 years ago

0 Neeraj Gill over 4 years ago

TI__Mastermind 20541 points

Hi Kate,

We are looking at your question and will get back to you soon.

Regards,
Neeraj

0 jim s over 4 years ago

TI__Guru* 91947 points

Kate,

The SYNC is active high on this part which is the opposite per the standard. We invert this signal inside our firmware when using this part.

Regards,

Jim

0 Kate Rayhman over 4 years ago in reply to jim s

Prodigy 40 points

Hi Jim,
I will try to reverse the sync inside the FPGA before it is sent out.
But can you explain where is it reversed? before entering the ADS42JB69?
So if we use our own custom board in the future, I should reverse it back?

0 jim s over 4 years ago in reply to Kate Rayhman

TI__Guru* 91947 points

Kate,

The FPGA would invert the SYNC before sending it to the ADC.

Regards,

Jim

0 Kate Rayhman over 4 years ago in reply to jim s

Prodigy 40 points

Hi Jim, can we talk offline?
I still can't quite understand how this is implemented.
The sync should be active low (as in ADS42JB69 spec).
The Xilinx IP drives it as active low.
When is it inverted?

0 jim s over 4 years ago in reply to Kate Rayhman

TI__Guru* 91947 points

Kate,

The FPGA JESD IP block will send out an active low SYNC signal after power up. Before this signal leaves the FPGA, we add an inverter that inverts the SYNC so that it becomes a high. Upon receiving a high SYNC signal, the ADC enters the CGS cycle and starts transmitting the K28.5 characters. Once the FPGA detects 4 consecutive K28.5 on all lanes, it will send SYNC high. Since this signal then gets inverted, the ADC will see a low SYNC and will start the ILA sequence.

The data sheet has this shown incorrectly. Sorry about the confusion.

Regards,

Jim

0 Kate Rayhman over 4 years ago in reply to jim s

Prodigy 40 points

Thanks Jim.
I inverted the sync in the FPGA and it seems to work better.
Kate

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ADS42JB69EVM: ADS42JB69EVM not sending sync codes when sync is driven low.