Other Parts Discussed in Thread: DAC38J84, LMK04828
HI,
We are using JESD204B IP core (XILINX).
Ip core : JESD204(7.2)
application : Data transfer from FPGA(virtex - 7 (VC709) ) to DAC(DAC38J84) through JESD204B protocol at line rate of 6.4 Gbps.
configuration done on FPGA side.
We are using reference clock of 160 MHz.
so our line rate will be = (reference clock * 40) = 160MHz * 40 = 6.4 Gbps.
configuration of line rate and reference clock is made from JESD204 PHY configuration tab of JESD204(7.2) IP core.
using the DAC EVM gui for DAC38J84 to configure the JESD204B we have a onboard oscillator 122.88 MHz.
The the jitter cleaner IC LMK04828 is used generate clock and provide the CLOCK and SYREF to DAC and FPGA.
using onboard clock we are able to configure using the quik start tab and the line rate we can get closest to 6.4Gbps is 6.144Gbps.
clock generated for FPGA is 153.6 MHz.
what we need is to match the line rate between FPGA and DAC. Is it possible to generate 160MHz clock from LMK04828 by using
the reference clock of 122.88 MHz?
formula used to find device clock = Vin(refrence clock) * N (Divider) * P (Prescalar) / divider value.
Example = Vin = 122.88 N=10 p=2 divider value = 16
device clock = 122.88 * 10 * 2 / 16
= 2457.6 / 16
= 153.6
Thanks and Regards
Suraj
