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DAC38J84EVM: Interfacing DAC38J84 with KC705

Part Number: DAC38J84EVM
Other Parts Discussed in Thread: DAC38J84

hi,

We are having the DAC EVM DAC38J84 and KC705 evaluation board.
we want to implement the reference design slac690c which implements the  JESD204B interface


To work with this reference design we need the TSW14J10 FMC-USB Interposer Card to communicate
with the HSDC pro software.

at present we have only the DAC38J84 EVM and KC705 EVM( XILINX FPGA).
we need to remove the functionality of TWS14J10 from the reference design.

to do the above process we need answers for the following quaries

1 . What are signals going from HSDC pro software to FPGA trough SPI interface?
     and what is the JESD204B configuration it is sending to FPGA?
     and how do we configure JESD204b ip without the TSW14J10 board in the reference design?

2. we are programming the DACEVM register using the DAC GUI. but it is
    mentioned in the TSW14J10 user guide that using HSDC pro is able
   to control the register of DAC .
   what is the configuration that is written into DAC EVM using the HSDC pro ?

3. without using TSW14J10 can we use HSDC pro software to collect ADC data or
    send pattern to DAC?

Thanks and Regards
Suraj Gaonkar

  • Hi Suraj,

    We are taking a looking into your questions, and will be back with you soon.

    Best Regards,

    Dan

  • Suraj,

    1 . What are signals going from HSDC pro software to FPGA trough SPI interface? All of the signals on the USB I/F device U3. All other signals are connected between the two FMC connectors and just pass through the TSW14J10.  See attached schematic.


         and what is the JESD204B configuration it is sending to FPGA? Depends on what mode is used by the DAC.


         and how do we configure JESD204b ip without the TSW14J10 board in the reference design? You will have to program the FPGA using either the USB interface or JTAG connector on the KC705 board.

    2. we are programming the DACEVM register using the DAC GUI. but it is
        mentioned in the TSW14J10 user guide that using HSDC pro is able
       to control the register of DAC .
       what is the configuration that is written into DAC EVM using the HSDC pro ? HSDC Pro cannot program the DAC. If it was mentioned, this was an error in the User's Guide. There is an option to control the SPI pins on the DAC EVM across the FMC, but it would be up the user to develop this interface in their firmware.

    3. without using TSW14J10 can we use HSDC pro software to collect ADC data or
        send pattern to DAC? No.

    Regards,

    Jim

    3731.TSW14J10-SCH_C.pdf

  • hi Jim,

    I want to configure the  DAC38J84 EVM  with LMFS = 4421 .

     for the above configuration  

    what is the JESD204B configuration HSDC pro needs to send to  FPGA through SPI interface ?

    What is the procedure to follow interfacing the  DAC38J84 EVM with KC705 EVM (FPGA)  without using the

    TSW14J10  card ?

    We need to use the reference design slac690c  but replace the part used by TSW14J10  card.

    Can you please help us finding the solution for above problem

    Thanks and regards

    Suraj Gaonkar

  • Suraj,

    You keep mentioning HSDC Pro and that you are not going to use the TSW14J10EVM. This is not an option. If you plan on using HSDC pro, you will need the TSW14J10EVM.

    I would suggest you go the Xilinx website and download the example firmware they provide. If you provide us with the following information, I can send you a  DAC register setting file you can load using the DAC EVM GUI.

    1. DAC sample rate

    2. FPGA data rate and reference clock frequency

    3. K value

    4. SYSREF frequency

    5. Interpolation factor

    6. NCO frequency if you plan on using it.

    Regards,

    Jim 

  • hi Jim,

    i need the the configuration of JESD204B IP in FPGA which is done by HSDC pro software through SPI interface.

    so that i can configure the JESD204B IP through FPGA itself without needing the help of HSDC pro software.

    below are the details asked for 

    1. DAC sample rate = 320 MHz

    2. FPGA data rate and reference clock frequency = 160 MHz

    3. K value =20

    4. SYSREF frequency = 

    5. Interpolation factor = 1

    6. NCO frequency if you plan on using it. = not using

    Thanks and Regards

    Suraj Gaonkar

  • Suraj,

    The DAC configuration file and setup file are attached. The setup file shows the FPGA JESD204B configuration used by the FPGA. The firmware that gets loaded by HSDC Pro uses both a reference clock and core clock. For more information regarding this, see attached file from Xilinx and the TSW14J10EVM User's Guide, which can be found under the TSW14J10EVM product folder on the TI website.

    Regards,

    Jim

    7673.JESD204_TI_reference_design.pdf

    DAC38J84_442_320.pptx

    LMF_4421.cfg

     

  • Hi Jim,

    In  JESD204_TI_reference_design.pdf  page 15. 

    they have mentioned about he Writeable bank addressing

    Bank0 , Bank1 and Bannk2 

    i need the register value written on these bank.  

    and also the procedure to access these banks in the reference design.

    Thanks and Regards

    Suraj Gaonkar

  • Suraj,

    You will have to contact Xilinx regarding this as they developed this firmware for us and wrote this document.

    Regards,

    Jim