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ADC12D1620QML-SP: Input Sample Clock Derived From LMX2615-SP

John Roy94
Prodigy 180 points
Part Number: ADC12D1620QML-SP
Other Parts Discussed in Thread: LMX2615-SP, TSW12D1620EVM-CVAL, LMX2594

Hello, 

We wish to provide the sample clock to two ADC12D1620QML-SP devices using one LMX2615-SP device (using the RFoutA and RFoutB outputs)  


1. Has anyone done this, at least for one channel, and can provide performance data (i.e. ENOB) from the ADC? Most concerned about internally generated spurs due to input clock

2. What is the required termination between the LMX2615 device and the ADC12D1620 clock inputs? Is a transformer required, DC network, AC coupling, etc? 

3. Is a band pass filter recommended for the input clock to minimize harmonics of the input clock? 

4. Is there a reference design or block diagrams that show the interconnections?

Regards,

John

  • 0
    TI__Mastermind 43920 points

    Hi John

    This configuration will work OK, but I don't have any data from this exact combination of devices.

    1) What approximate frequency range will you be supplying to the ADC, and what reference clock with the LMX2615-SP be receiving? This will determine what mode the LMX device is operated in. In general I wouldn't expect significant spurs in the ADC spectrum if the LMX is operating in integer mode and both outputs are at the same frequency. I have encountered issues in the past when the LMX outputs are at different frequencies. Cross talk between the outputs can cause issues in that configuration. 

    2) I would recommend the 50 ohm resistive pull-up termination discussed in section 8.1.4 of the LMX2615-SP datasheet. Use AC-coupling capacitors to connect the LMX2615-SP outputs to the ADC12D1620QML-SP CLK+/- inputs. Ensure the capacitor values are large enough to present minimal series impedance at the lowest clock frequency of interest.

    3) This should not be necessary with this ADC and for the input signal and clock frequencies used in this application.

    4) Please refer to sheets 3 and 6 of the TSW12D1620EVM-CVAL schematics available here: http://www.ti.com/lit/pdf/sbar002 We included the LMX2615-SP in this reference design but have not validated this portion of the circuitry yet. Since it is very similar to our usage of the LMX2594 on other platforms in the past I am confident this termination scheme will work. 

    Please note that if you plan to synchronize sampling and output data between the two ADC12D1620QML-SP devices you should add the needed AutoSync connections to the board design. One ADC will be configured as a master device, and the other as a slave device. RCOut1 or RCOut2 of the master will connect to RCLK of the slave. Add test points on the ADC DCLK output buses to support the required AutoSync tuning procedure. The AutoSync feature is described in detail in section 8.1.4 of the ADC12D1620QML-SP datasheet.

    Best regards,

    Jim B