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ADS8320: about big glitches in Vin of ADS8320

Vera Mao
Expert 5065 points
Part Number: ADS8320

hi dear supporting team,

customer is using ADS8320 with below sch(share the same circuit with AD7683).  They found there is close to 1V glitch at Vin pin, which has same cycle with Cs signal.   the input is disconnect with previous stage. and the sample rate is several 10KHz, Vref is 2.5V. I checked the sch, seems only decoupling cap mis-match with our recommend sch, will that be a issue? any other possible cause? tks a lot!

the CS and the glitch detect at Vin: blue is Vin, yellow is CS.

the CS&CLK timing：

  • 0
    TI__Guru 62846 points

    Hello Vera,

    Thank you for supporting our ADS8320.

    I suppose that somehow the /CS signal is coupling onto the ground plane, which is then connected to IN+ through the 25k resistor. Can the customer remove this resistor (R152A3) to confirm?

    What is the reason for the resistor dividers on the digital input signals? Is the customer performing level-translation with these components? This will likely cause the ground to be very noisy and couple onto the inputs and supply pins.

    Best regards,

  • 0 in reply to Ryan Andrews
    TI__Expert 5065 points

    Hi Ryan,

    thank you for the reply! for those components marked as "True" in the sch, it is not soldered in the real brd.  so R152A3 is not soldered actually. 

    for those digital dividers, yes, it is for level shift.  customer has removed those pull down, and the issue is still there.

    I have asked them using external power supply for power and Vref, but no improvement.

    below is the layout information, the yellow dot is the  1st pin. pls help check whether you could find something.  and any other suggestion? 

    tks a lot! 

  • 0 in reply to Vera Mao
    TI__Guru 62846 points

    Hello Vera,

    Thank you for providing the layout. 

    How is the ground connected on the board? Is there an internal ground plane?

    Vera Mao said:
    customer has removed those pull down, and the issue is still there.

    It seems that only the falling edge of CS_N has an effect on the input voltage. This seems to indicate that the VDD current sees a sudden increase when the interface in enabled. We should try to remove as many optional connections to VDD or GND as possible.

    Please confirm that all of the following pull-down/pull-up resistors have been removed for now:

    1. R150A3 (disconnect input circuit)
    2. R152A3 (IN+/-)
    3. R158A3 (CS_N)
    4. R160A3 (DCLOCK)
    5. R165A3 (DCLOCK)
    6. R179A3 (DOUT)
    7. R206A3 (VREF)

    In addition, try shorting the ferrite bead in series with VDD (L37A3).

    After these modifications, probe IN+ and IN- separately and let me know the result.

    Regards,

  • 0 in reply to Ryan Andrews
    TI__Expert 5065 points

    Hi Ryan,

    Thank you very much for the reply !

    The ground is connected from PIN3,4 through via to 2nd layer which is  GND layer.

    Yes, those resistors are removed, and also when doing external power supply, the ferrite bead are shorted. But the phenomenon is still the same. Is there any opportunity that you could help check on the EVM to see whethere there is same issue?  We are also applying Eva, but haven't received yet.

  • 0 in reply to Vera Mao
    TI__Guru 62846 points

    Hi Vera,

    Maybe this glitch is caused by the input sampling. Is there any capacitance on the +IN signal path? What is driving "VOLTAGE_LPDETCET1"?

    Typically there is a capacitor between the inputs to provide instantaneous current during sampling. Can the customer try installing a 1-nF capacitor in place of R152A3? Then, install R150A3 and drive the +IN pin to a known DC voltage. You might need to change R150A3 from 0 ohms to 10 - 100 ohms to maintain stability if there is an amplifier driving this input.

    Best regards,