hi,
i what to sample a fast single pulse analog signal .
sample rate 100MSPS with ADS4125 Parallel CMOS Interface
an FPGA is interface with the A2D
i want to connect a lvcmos 100Mhz clk to the FPGA and A2D
the A2D and the FPGA need to be clk synchronize
questions
1. can i use one low jitter clk 100Mhz 1.8V connected to zero delay buffer 1:2 (1 in , 2 out)
the zero delay buffer will drive 1.8v 100mhz clk to the FPGA and the A2D
2.to sample a fast single pulse is it a problem to use a single ended clk in insted of differantial clk
3. VCM is connected to CLKM is single ended clk input
will VCM be noisy because of that?
regards
pablo