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DAC7551-Q1: Serial Write Operation Timing

Part Number: DAC7551-Q1
Other Parts Discussed in Thread: DAC7551

 

Hi technical support of TI

We are interested in your DAC7551-Q1. We want to use SPI interface to access it. But we have a question about its Serial Write Operation Timing.

  • The datasheet says that the t7 (SCLK falling edge to SYNC rising edge time) should not exceed (t1 – 10 ns) to latch the correct data. This requirement seems not to be a normal requirement in the SPI protocol. From my perspective, t7 is a hold time so it should has the minimum instead of the maximum. If we write 16 bits data to the DAC only once, and then SCLK keeps high, can the t7 exceed (t1 – 10 ns) in this senario?

  • Hello,

    Welcome to E2E and thank you for your query. Note that t7 is specified before the last half-cycle of the SCLK. The minimum value is 0. So, you don't it in case of mode 1 of SPI. However, in mode 2, I see that this may pose some problems in case you are using a standard SPI interface. If you are unable use mode 2 with these constraints, please try using mode 1.

    Hope that answers your question.

    Regards,

    Uttam Sahu

    Applications Engineer, Precision DACs

  • Hi,

    Thank you for your reply, but I am still confused at 2 aspects below

    • The SPI mode 1 means CPOL= 0, CPHA=1 and SPI mode 2 means CPOL=1, CPHA=0. Correct?
    • In the DAC7551's timing diagram, the SPI works in mode 2. Is DAC7551 compatible with mode 1. Where is it mentioned in datasheet? 

  • Hi,

    1. That is correct.  Please refer to the below figure, borrowed from wikipedia.

    2. Most SPI devices can work in two modes.  The critical configuration is that the data is latched on the falling edge of SCLK, and that the MOSI line is valid on the first edge.  That is why mode 01 and mode 10 work. We try to indicate this by showing both clock states before the falling edge of CS in the timing diagram. Note the solid clock 'high' and the clock toggling curves overlaid on timing diagram.

    Thanks,

    Paul