DAC80004: DAC80004IPW query & CLR pin

Hello,

If the device appears to be functional for both zero-scale and mid-scale POR settings, most likely the issue is in the digital domain. Can you share an oscilloscope capture showing the complete SPI transaction you are using to attempt to set the DAC output code?

Hi Kevin,

Thanks for your response. Please find attached the SPI transactions waveforms(Full capture as well as first to fourth byte waveforms)

Command : 0x03 0f ff f0

Tested for all channels : A,B,C,D. The attached waveform is for channel A.

Would you like to comment on the floating CLR pin? This needs to be pulled high? 

I look forward your response as soon as possible.

Regards,

AT

AT,

Somehow I missed the comment towards the floating CLR pin in my original reply. While technically the pin is falling edge sensitive it is not suggested to leave it floating if the pin is not in use and certainly tying it to VDD would be a worthwhile experiment to check if your device is unintentionally being held in the clear state.

What are your clock phase and polarity settings for your MCU? I cannot quite make out the timing due to the scale of the plots, but it looks like data is changing on SDIN at around the same time as the falling clock edge. Data is shifted into the device on the falling edge of SCLK, so there is some risk that invalid or unintended data is being latched and therefore you are not seeing the desired results at the output. Generally speaking for a falling edge critical interface I would expect to see data change on the rising edge so that setup and hold timings are met, so maybe your fix is as simple as changing CPOL and CPHA settings.