Hi DC team,
I'm posting this question on behalf of my customer. These questions are regarding ADS125H01.
1. We want to run it (CLKIN) from 2.048 MHz derived from our phase locked to GPS TCXO. It would be configured to produce 40,000 sps but the actual data rate would be 8000 sps since the clock is reduced by 5X. Is this a valid configuration?
2. It appears that to read the conversion value, the RDATA command sequence must be issued when DRDY- is asserted. Is this correct? The RDATA exchange is 9 bytes. That is a lot to get 3 bytes of ADC conversion data.
3. It also appears that the chip is not designed to “cascade” them so three ADCs would require only one SPI interface. Is this correct? The 3 ADCs would be STARTED at the same time so their DRDY- outputs should happen concurrently. If this is so, we would have to use an FPGA or CPLD to perform the RDATA commands in hardware then get the data into the MSP430 via one long SPI DMA transfer. We would rather not do that. It adds cost and complexity.
4. Can the SPI SCLK really be run at 10.24 MHz when CLKIN is running at 2.048 MHz? Many devices require that the SCLK be run at less than or equal to the system clock.