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ADS125H01: When does ADS125H01 plan to RTM and further questions

Part Number: ADS125H01

Hi DC team,

I'm posting this question on behalf of my customer. These questions are regarding ADS125H01.

1. We want to run it (CLKIN) from 2.048 MHz derived from our phase locked to GPS TCXO. It would be configured to produce 40,000 sps but the actual data rate would be 8000 sps since the clock is reduced by 5X. Is this a valid configuration?

2. It appears that to read the conversion value, the RDATA command sequence must be issued when DRDY- is asserted. Is this correct? The RDATA exchange is 9 bytes. That is a lot to get 3 bytes of ADC conversion data.

3. It also appears that the chip is not designed to “cascade” them so three ADCs would require only one SPI interface. Is this correct? The 3 ADCs would be STARTED at the same time so their DRDY- outputs should happen concurrently. If this is so, we would have to use an FPGA or CPLD to perform the RDATA commands in hardware then get the data into the MSP430 via one long SPI DMA transfer. We would rather not do that. It adds cost and complexity.

4. Can the SPI SCLK really be run at 10.24 MHz when CLKIN is running at 2.048 MHz? Many devices require that the SCLK be run at less than or equal to the system clock.

  • Hi Lauren,

    1. Yes, this is valid...
      At the 40 kSPS data rate you can use an external clock between 1 and 10.75 MHz, as given in the "Recommended Operating Conditions" table. One downside to running the ADC in this way (rather than using the 7200 data rate), is that the digital filter latency will be a little longer (0.72ms vs 0.51ms from start of conversion to first /DRDY falling edge).
    2. /DRDY low indicates that the ADC has completed a conversion, so typically a falling-edge GPIO interrupt can be configured on the MCU to retrieve the ADC data. The full RDATA command is 9 bytes when the STATUS byte is enabled. The STATUS byte can optionally be disabled by programming the MODE3 register to shorten this command to 8 bytes, but the CRC error checking on the SPI still adds significant overhead to the command.

    3. A single SPI peripheral can be used to talk to three ADS125H01's, but you would want to have separate GPIOs to control each of the /CSx pins. It would still be three separate RDATA commands (one to each ADC) to retrieve all the data. I'm not very familiar with using the SPI DMA on the MSP430, but you may not be able to use the DMA if the SPI command exceeds more than 2 bytes anyways.

    4. Yes! The SPI clock and the internal system clock are decoupled in this ADC. In older devices, the SPI clock would generally have to be slower.